Searched refs:MISCREG_HSR (Results 1 - 4 of 4) sorted by relevance

/gem5/src/arch/arm/
H A Dmiscregs.hh217 MISCREG_HSR, enumerator in enum:ArmISA::MiscRegIndex
H A Dfaults.cc591 setSyndrome(tc, MISCREG_HSR);
596 setSyndrome(tc, MISCREG_HSR);
H A Dmiscregs.cc317 return MISCREG_HSR;
3321 InitReg(MISCREG_HSR)
4136 .mapsTo(MISCREG_HSR);
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc194 { "hsr", MISCREG_HSR },

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