Searched refs:MISCREG_FSW (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/x86/
H A Disa.cc145 if (miscReg == MISCREG_FSW) {
146 RegVal fsw = regVal[MISCREG_FSW];
171 case MISCREG_FSW:
/gem5/src/arch/x86/regs/
H A Dmisc.hh384 MISCREG_FSW, enumerator in enum:X86ISA::MiscRegIndex
/gem5/src/cpu/kvm/
H A Dx86_cpu.cc828 // No need to rebuild from MISCREG_FSW and MISCREG_TOP if we read
830 fpu.fsw = tc->readMiscReg(MISCREG_FSW);
1061 tc->setMiscRegNoEffect(MISCREG_FSW, fpu.fsw);

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