Searched refs:MISCREG_EPC (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/mips/
H A Dregisters.hh188 MISCREG_EPC = 112, //Bank 14: 112-119 enumerator in enum:MipsISA::MiscRegIndex
H A Dfaults.cc123 tc->setMiscRegNoEffect(MISCREG_EPC,

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