Searched refs:MISCREG_ENTRYLO0 (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/mips/ | ||
| H A D | registers.hh | 147 MISCREG_ENTRYLO0 = 16, //Bank 2: 16 - 23 enumerator in enum:MipsISA::MiscRegIndex |
| H A D | isa.cc | 391 setRegMask(MISCREG_ENTRYLO0, mask); |
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