Searched refs:LSQ (Results 1 - 15 of 15) sorted by relevance

/gem5/src/cpu/o3/
H A Dlsq.cc35 template class LSQ<O3CPUImpl>;
H A Dlsq_impl.hh56 #include "debug/LSQ.hh"
63 LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params) function in class:LSQ
86 DPRINTF(LSQ, "LSQ sharing policy set to Dynamic\n");
88 DPRINTF(Fetch, "LSQ sharing policy set to Partitioned: "
96 DPRINTF(LSQ, "LSQ sharing policy set to Threshold: "
100 panic("Invalid LSQ sharing policy. Options are: Dynamic, "
115 LSQ<Imp
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H A Dcpu_policy.hh73 /** Typedef for the LSQ. */
74 typedef ::LSQ<Impl> LSQ; typedef in struct:SimpleCPUPolicy
75 /** Typedef for the thread-specific LSQ units. */
H A Diew.hh63 * instructions to the LSQ/IQ as part of the issue stage, and has the
73 * instructions from non-memory instructions, either telling the LSQ
90 typedef typename CPUPol::LSQ LSQ; typedef in class:DefaultIEW
147 /** Initializes stage; sends back the number of free IQ and LSQ entries. */
212 /** Resets entries of the IQ and the LSQ. */
229 /** Returns if the LSQ has any stores to writeback. */
232 /** Returns if the LSQ has any stores to writeback. */
260 /** Dispatches instructions to IQ and LSQ. */
264 * LSQ t
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H A Dlsq.hh64 class LSQ class
74 /** Derived class to hold any sender state the LSQ needs. */
106 * LSQ entries can be squashed before the response comes back. in that
128 /** Pointer to LSQ. */
129 LSQ<Impl> *lsq;
134 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
170 * be a defined ownership transferal in case the LSQ resources are
177 * |LSQ creates and owns|
257 /** LSQ resources freed. */
369 * An LSQRequest manages itself when the resources on the LSQ ar
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H A Dlsq_unit.hh77 * the LSQ until the store writes back. At that point the load is
89 typedef typename Impl::CPUPol::LSQ LSQ; typedef in class:LSQUnit
92 using LSQSenderState = typename LSQ::LSQSenderState;
93 using LSQRequest = typename Impl::CPUPol::LSQ::LSQRequest;
217 /** Constructs an LSQ unit. init() must be called prior to use. */
226 /** Initializes the LSQ unit with the specified number of entries. */
228 LSQ *lsq_ptr, unsigned id);
230 /** Returns the name of the LSQ unit. */
252 /** Check for ordering violations in the LSQ
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H A Dcpu.hh129 using LSQRequest = typename LSQ<Impl>::LSQRequest;
713 /** CPU pushRequest function, forwards request to LSQ. */
725 /** CPU read function, forwards read to LSQ. */
731 /** CPU write function, forwards write to LSQ. */
H A Dlsq_unit_impl.hh157 LSQ *lsq_ptr, unsigned id)
/gem5/src/cpu/minor/
H A Dlsq.cc59 LSQ::LSQRequest::LSQRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_,
78 LSQ::LSQRequest::tryToSuppressFault()
97 LSQ::LSQRequest::completeDisabledMemAccess()
114 LSQ::LSQRequest::disableMemAccess()
120 LSQ::AddrRangeCoverage
121 LSQ::LSQRequest::containsAddrRangeOf(
142 LSQ::AddrRangeCoverage
143 LSQ::LSQRequest::containsAddrRangeOf(LSQRequestPtr other_request)
150 LSQ
1393 LSQ::LSQ(std::string name_, std::string dcache_port_name_, function in class:Minor::LSQ
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H A Dlsq.hh61 class LSQ : public Named class in namespace:Minor
93 LSQ &lsq;
96 DcachePort(std::string name, LSQ &lsq_, MinorCPU &cpu) :
126 LSQ &port;
199 LSQRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_,
308 SpecialDataRequest(LSQ &port_, MinorDynInstPtr inst_) :
320 FailedDataRequest(LSQ &port_, MinorDynInstPtr inst_) :
333 BarrierDataRequest(LSQ &port_, MinorDynInstPtr inst_) :
375 SingleDataRequest(LSQ &port_, MinorDynInstPtr inst_,
420 SplitDataRequest(LSQ
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H A Dexecute.hh61 * The LSQ lives here too. */
116 LSQ lsq;
166 /** In-order instructions either in FUs or the LSQ */
233 LSQ::LSQRequestPtr response, BranchData &branch,
238 * memory access to the LSQ.
240 * because of a lack of LSQ resources and false otherwise.
330 /** To allow ExecContext to find the LSQ */
331 LSQ &getLSQ() { return lsq; }
H A Dexecute.cc322 LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault)
741 * queue to ensure in-order issue to the LSQ */
783 /* Mark up barriers in the LSQ */
1049 * 1) Responses returning from the LSQ
1050 * 2) Mem ops issued to the LSQ ('committed' from the FUs) earlier
1111 LSQ::LSQRequestPtr mem_response =
1156 * - Can push a request into the LSQ
1173 * to 'commit'/send to the LSQ */
1219 * mem refs on their way to the LSQ */
1329 /* Mark the mem inst as being in the LSQ */
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/gem5/ext/mcpat/
H A Dcore.cc798 : McPATComponent(_xml_data), dcache(NULL), LSQ(NULL), LoadQ(NULL),
862 LSQ = new ArrayST(xml_data, &interface_ip, "Store Queue", Core_device,
864 area.set_area(area.get_area() + LSQ->local_result.area);
866 lsq_height = LSQ->local_result.cache_ht * sqrt(cdb_overhead);
902 lsq_height = (LSQ->local_result.cache_ht +
3027 LSQ->tdp_stats.reset();
3028 LSQ->tdp_stats.readAc.access = LSQ->l_ip.num_search_ports *
3030 LSQ->tdp_stats.writeAc.access = LSQ
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H A Dcore.h189 ArrayST* LSQ; member in class:LoadStoreU
/gem5/src/cpu/
H A Dbase_dyn_inst.hh86 using LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest*;
106 LsqEntry, /// Instruction is in the LSQ
117 SquashedInLSQ, /// Instruction is squashed in the LSQ
332 /** True if the address hit a external snoop while sitting in the LSQ.
802 /** Sets this instruction as a entry the LSQ. */
805 /** Sets this instruction as a entry the LSQ. */
808 /** Returns whether or not this instruction is in the LSQ. */
811 /** Sets this instruction as squashed in the LSQ. */
814 /** Returns whether or not this instruction is squashed in the LSQ. */

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