Searched refs:LR (Results 1 - 5 of 5) sorted by relevance

/gem5/src/dev/arm/
H A Dvgic.hh47 * The mode in which the List Registers may flag (via LR.HW) that a hardware EOI
163 std::fill(LR.begin(), LR.end(), 0);
167 std::array<ListReg, NUM_LR> LR; member in struct:VGic::vcpuIntData
226 if (vid->LR[i].State & LR_PENDING)
235 if (vid->LR[i].State)
241 /** Returns LR index or -1 if none pending */
247 if ((vid->LR[i].State & LR_PENDING) && (vid->LR[i].Priority < prio)) {
249 prio = vid->LR[
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H A Dvgic.cc116 ListReg *lr = &vid->LR[i];
123 panic("VGIC does not support 'HW' List Register feature (LR %#x)!\n",
126 DPRINTF(VGIC, "Consumed interrupt %d (cpu%d) from LR%d (EOI%d)\n",
202 if (!vid->LR[i].State)
211 if (!vid->LR[i].State)
226 pkt->setLE<uint32_t>(vid->LR[(daddr - GICH_LR0) >> 2]);
265 DPRINTF(VGIC, "EOIR: No LR for irq %d(cpu%d)\n", virq, vcpu);
267 DPRINTF(VGIC, "EOIR: Found LR%d for irq %d(cpu%d)\n", i, virq, vcpu);
268 ListReg *lr = &vid->LR[i];
335 vid->LR[(dadd
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/gem5/util/statetrace/arch/arm/
H A Dtracechild.hh68 R8, R9, R10, FP, R12, SP, LR, PC, enumerator in enum:ARMTraceChild::RegNum
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ua/
H A Dlrsc.S7 # Test LR/SC instructions.
/gem5/ext/systemc/src/sysc/qt/md/
H A Dhppa_b.s56 addil LR'to_call-$global$,%r27

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