Searched refs:IcachePort (Results 1 - 7 of 7) sorted by relevance

/gem5/src/cpu/minor/
H A Dfetch1.hh65 class IcachePort : public MinorCPU::MinorCPUPort class in class:Minor::Fetch1
72 IcachePort(std::string name, Fetch1 &fetch_, MinorCPU &cpu) : function in class:Minor::Fetch1::IcachePort
204 /** IcachePort to pass to the CPU. Fetch1 is the only module that uses
206 IcachePort icachePort;
394 /** Returns the IcachePort owned by this Fetch1 */
/gem5/src/cpu/o3/
H A Dfetch.hh91 * IcachePort class for instruction fetch.
93 class IcachePort : public MasterPort class in class:DefaultFetch
101 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) function in class:DefaultFetch::IcachePort
544 IcachePort icachePort;
H A Dfetch_impl.hh1678 DefaultFetch<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
1691 DefaultFetch<Impl>::IcachePort::recvReqRetry()
/gem5/src/cpu/simple/
H A Dtiming.hh186 class IcachePort : public TimingCPUPort class in class:TimingSimpleCPU
190 IcachePort(TimingSimpleCPU *_cpu) function in class:TimingSimpleCPU::IcachePort
256 IcachePort icachePort;
H A Dtiming.cc845 TimingSimpleCPU::IcachePort::ITickEvent::process()
851 TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
864 TimingSimpleCPU::IcachePort::recvReqRetry()
/gem5/src/cpu/trace/
H A Dtrace_cpu.hh226 * IcachePort class that interfaces with L1 Instruction Cache.
228 class IcachePort : public MasterPort class in class:TraceCPU
232 IcachePort(TraceCPU* _cpu) function in class:TraceCPU::IcachePort
323 IcachePort icachePort;
H A Dtrace_cpu.cc1217 TraceCPU::IcachePort::recvTimingResp(PacketPtr pkt)
1227 TraceCPU::IcachePort::recvReqRetry()

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