Searched refs:INTRLVREG0 (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/arm/ |
| H A D | registers.hh | 101 const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs; member in namespace:ArmISA
102 const int INTRLVREG1 = INTRLVREG0 + 1;
103 const int INTRLVREG2 = INTRLVREG0 + 2;
104 const int INTRLVREG3 = INTRLVREG0 + 3;
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| /gem5/src/arch/arm/insts/ |
| H A D | sve_macromem.hh | 73 mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
144 mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
150 mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
217 mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
289 mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
295 mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
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