Searched refs:GICR_ISENABLER0 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_redistributor.hh113 GICR_ISENABLER0 = SGI_base + 0x0100, enumerator in enum:Gicv3Redistributor::__anon10
H A Dgic_v3_redistributor.cc227 case GICR_ISENABLER0: // Interrupt Set-Enable Register 0
454 case GICR_ISENABLER0: // Interrupt Set-Enable Register 0

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