Searched refs:GICC_CTLR (Results 1 - 4 of 4) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v2.hh95 GICC_CTLR = 0x00, // CPU control register enumerator in enum:GicV2::__anon123
345 * 2) GICC_CTLR.FIQEn: controls whether the CPU interface signals Group 0
360 * Checks if GICC_CTLR.EnableGrp0 or EnableGrp1 are set
367 /** GICC_CTLR:
H A Dgic_v3_cpu_interface.hh166 GICC_CTLR = 0x0000, enumerator in enum:Gicv3CPUInterface::__anon5
H A Dgic_v2.cc314 case GICC_CTLR:
579 case GICC_CTLR:
/gem5/src/arch/arm/kvm/
H A Dgic.cc349 copyCpuRegister(from, to, ctx, GICC_CTLR);

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