Searched refs:Fetch1 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/cpu/minor/
H A Dfetch1.cc55 Fetch1::Fetch1(const std::string &name_, function in class:Minor::Fetch1
116 Fetch1::getScheduledThread()
148 Fetch1::fetchLine(ThreadID tid)
211 operator <<(std::ostream &os, Fetch1::IcacheState state)
214 case Fetch1::IcacheRunning:
217 case Fetch1::IcacheNeedsRetry:
228 Fetch1::FetchRequest::makePacket()
240 Fetch1::FetchRequest::finish(const Fault &fault_, const RequestPtr &request_,
253 Fetch1
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H A Dfetch1.hh43 * Fetch1 is responsible for fetching "lines" from memory and passing
61 class Fetch1 : public Named class in namespace:Minor
69 Fetch1 &fetch;
72 IcachePort(std::string name, Fetch1 &fetch_, MinorCPU &cpu) :
107 Fetch1 &fetch;
170 FetchRequest(Fetch1 &fetch_, InstId id_, TheISA::PCState pc_) :
204 /** IcachePort to pass to the CPU. Fetch1 is the only module that uses
298 /** Queue of address translated requests from Fetch1 */
322 Fetch1::FetchState state);
385 Fetch1(cons
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H A Dpipeline.hh88 Fetch1 fetch1;
137 /** Return the IcachePort belonging to Fetch1 for the CPU */

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