Searched refs:CSR_STVEC (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh316 CSR_STVEC = 0x105, enumerator in enum:RiscvISA::CSRIndex
487 {CSR_STVEC, {"stvec", MISCREG_STVEC}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h788 #define CSR_STVEC 0x105 macro
1280 DECLARE_CSR(stvec, CSR_STVEC)

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