Searched refs:CSR_STVAL (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh321 CSR_STVAL = 0x143, enumerator in enum:RiscvISA::CSRIndex
492 {CSR_STVAL, {"stval", MISCREG_STVAL}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h793 #define CSR_STVAL 0x143 macro
1285 DECLARE_CSR(stval, CSR_STVAL)

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