Searched refs:CSR_SSTATUS (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh312 CSR_SSTATUS = 0x100, enumerator in enum:RiscvISA::CSRIndex
483 {CSR_SSTATUS, {"sstatus", MISCREG_STATUS}},
725 {CSR_SSTATUS, SSTATUS_MASK},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h786 #define CSR_SSTATUS 0x100 macro
1278 DECLARE_CSR(sstatus, CSR_SSTATUS)

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