Searched refs:CSR_SIE (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh315 CSR_SIE = 0x104, enumerator in enum:RiscvISA::CSRIndex
486 {CSR_SIE, {"sie", MISCREG_IE}},
726 {CSR_SIE, SI_MASK},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h787 #define CSR_SIE 0x104 macro
1279 DECLARE_CSR(sie, CSR_SIE)

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