Searched refs:CSR_SEPC (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh319 CSR_SEPC = 0x141, enumerator in enum:RiscvISA::CSRIndex
490 {CSR_SEPC, {"sepc", MISCREG_SEPC}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h791 #define CSR_SEPC 0x141 macro
1283 DECLARE_CSR(sepc, CSR_SEPC)

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