Searched refs:CSR_SCAUSE (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh320 CSR_SCAUSE = 0x142, enumerator in enum:RiscvISA::CSRIndex
491 {CSR_SCAUSE, {"scause", MISCREG_SCAUSE}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h792 #define CSR_SCAUSE 0x142 macro
1284 DECLARE_CSR(scause, CSR_SCAUSE)

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