Searched refs:CSR_MTVEC (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh334 CSR_MTVEC = 0x305, enumerator in enum:RiscvISA::CSRIndex
505 {CSR_MTVEC, {"mtvec", MISCREG_MTVEC}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h801 #define CSR_MTVEC 0x305 macro
1293 DECLARE_CSR(mtvec, CSR_MTVEC)

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