Searched refs:CSR_MISA (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh330 CSR_MISA = 0x301, enumerator in enum:RiscvISA::CSRIndex
501 {CSR_MISA, {"misa", MISCREG_ISA}},
729 {CSR_MISA, MISA_MASK},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h797 #define CSR_MISA 0x301 macro
1289 DECLARE_CSR(misa, CSR_MISA)

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