Searched refs:CSR_MHPMEVENT27 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh417 CSR_MHPMEVENT27 = 0x33B, enumerator in enum:RiscvISA::CSRIndex
587 {CSR_MHPMEVENT27, {"mhpmevent27", MISCREG_HPMEVENT27}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h890 #define CSR_MHPMEVENT27 0x33b macro
1382 DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)

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