Searched refs:CSR_MHPMEVENT26 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh416 CSR_MHPMEVENT26 = 0x33A, enumerator in enum:RiscvISA::CSRIndex
586 {CSR_MHPMEVENT26, {"mhpmevent26", MISCREG_HPMEVENT26}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h889 #define CSR_MHPMEVENT26 0x33a macro
1381 DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)

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