Searched refs:CSR_MHPMEVENT25 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh415 CSR_MHPMEVENT25 = 0x339, enumerator in enum:RiscvISA::CSRIndex
585 {CSR_MHPMEVENT25, {"mhpmevent25", MISCREG_HPMEVENT25}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h888 #define CSR_MHPMEVENT25 0x339 macro
1380 DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)

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