Searched refs:CSR_MHPMEVENT22 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh412 CSR_MHPMEVENT22 = 0x336, enumerator in enum:RiscvISA::CSRIndex
582 {CSR_MHPMEVENT22, {"mhpmevent22", MISCREG_HPMEVENT22}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h885 #define CSR_MHPMEVENT22 0x336 macro
1377 DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)

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