Searched refs:CSR_MHPMEVENT20 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh410 CSR_MHPMEVENT20 = 0x334, enumerator in enum:RiscvISA::CSRIndex
580 {CSR_MHPMEVENT20, {"mhpmevent20", MISCREG_HPMEVENT20}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h883 #define CSR_MHPMEVENT20 0x334 macro
1375 DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)

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