Searched refs:CSR_MHPMEVENT18 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh408 CSR_MHPMEVENT18 = 0x332, enumerator in enum:RiscvISA::CSRIndex
578 {CSR_MHPMEVENT18, {"mhpmevent18", MISCREG_HPMEVENT18}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h881 #define CSR_MHPMEVENT18 0x332 macro
1373 DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)

Completed in 11 milliseconds