Searched refs:CSR_MHPMEVENT10 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh400 CSR_MHPMEVENT10 = 0x32A, enumerator in enum:RiscvISA::CSRIndex
570 {CSR_MHPMEVENT10, {"mhpmevent10", MISCREG_HPMEVENT10}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h873 #define CSR_MHPMEVENT10 0x32a macro
1365 DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)

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