Searched refs:CSR_MHPMCOUNTER26 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh386 CSR_MHPMCOUNTER26 = 0xC1A, enumerator in enum:RiscvISA::CSRIndex
557 {CSR_MHPMCOUNTER26, {"mhpmcounter26", MISCREG_HPMCOUNTER26}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h860 #define CSR_MHPMCOUNTER26 0xb1a macro
1352 DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)

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