Searched refs:CSR_MHPMCOUNTER15 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh375 CSR_MHPMCOUNTER15 = 0xC0F, enumerator in enum:RiscvISA::CSRIndex
546 {CSR_MHPMCOUNTER15, {"mhpmcounter15", MISCREG_HPMCOUNTER15}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h849 #define CSR_MHPMCOUNTER15 0xb0f macro
1341 DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)

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