Searched refs:CSR_MHPMCOUNTER10 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh370 CSR_MHPMCOUNTER10 = 0xC0A, enumerator in enum:RiscvISA::CSRIndex
541 {CSR_MHPMCOUNTER10, {"mhpmcounter10", MISCREG_HPMCOUNTER10}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h844 #define CSR_MHPMCOUNTER10 0xb0a macro
1336 DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)

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