Searched refs:CSR_MEDELEG (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh331 CSR_MEDELEG = 0x302, enumerator in enum:RiscvISA::CSRIndex
502 {CSR_MEDELEG, {"medeleg", MISCREG_MEDELEG}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h798 #define CSR_MEDELEG 0x302 macro
1290 DECLARE_CSR(medeleg, CSR_MEDELEG)

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