Searched refs:CSR_HPMCOUNTER31 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh309 CSR_HPMCOUNTER31 = 0xC1F, enumerator in enum:RiscvISA::CSRIndex
481 {CSR_HPMCOUNTER31, {"hpmcounter31", MISCREG_HPMCOUNTER31}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h785 #define CSR_HPMCOUNTER31 0xc1f macro
1277 DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)

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