Searched refs:CSR_HPMCOUNTER30 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh308 CSR_HPMCOUNTER30 = 0xC1E, enumerator in enum:RiscvISA::CSRIndex
480 {CSR_HPMCOUNTER30, {"hpmcounter30", MISCREG_HPMCOUNTER30}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h784 #define CSR_HPMCOUNTER30 0xc1e macro
1276 DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)

Completed in 10 milliseconds