Searched refs:CSR_HPMCOUNTER18 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh296 CSR_HPMCOUNTER18 = 0xC12, enumerator in enum:RiscvISA::CSRIndex
468 {CSR_HPMCOUNTER18, {"hpmcounter18", MISCREG_HPMCOUNTER18}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h772 #define CSR_HPMCOUNTER18 0xc12 macro
1264 DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)

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