Searched refs:CSR_DPC (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh428 CSR_DPC = 0x7B1, enumerator in enum:RiscvISA::CSRIndex
598 {CSR_DPC, {"dpc", MISCREG_DPC}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h833 #define CSR_DPC 0x7b1 macro
1325 DECLARE_CSR(dpc, CSR_DPC)

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