Searched refs:CSR_CYCLE (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh278 CSR_CYCLE = 0xC00, enumerator in enum:RiscvISA::CSRIndex
450 {CSR_CYCLE, {"cycle", MISCREG_CYCLE}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h754 #define CSR_CYCLE 0xc00 macro
1246 DECLARE_CSR(cycle, CSR_CYCLE)

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