Searched refs:Branch (Results 1 - 16 of 16) sorted by relevance

/gem5/src/arch/sparc/insts/
H A Dbranch.hh39 // Branch instructions
48 class Branch : public SparcStaticInst class in namespace:SparcISA
60 class BranchDisp : public Branch
65 Branch(mnem, _machInst, __opClass), disp(_disp)
106 class BranchImm13 : public Branch
111 Branch(mnem, _machInst, __opClass),
H A Dbranch.cc36 // Branch instructions
47 Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
/gem5/src/cpu/pred/
H A Dbpred_unit.cc54 #include "debug/Branch.hh"
190 DPRINTF(Branch, "[tid:%i] [sn:%llu] "
200 DPRINTF(Branch, "[tid:%i] [sn:%llu] "
201 "Branch predictor predicted %i for PC %s\n",
210 DPRINTF(Branch, "[tid:%i] [sn:%llu] "
234 DPRINTF(Branch, "[tid:%i] [sn:%llu] Instruction %s is a return, "
248 DPRINTF(Branch,
260 DPRINTF(Branch,
265 DPRINTF(Branch, "[tid:%i] [sn:%llu] BTB doesn't have a "
273 DPRINTF(Branch,
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H A Dmultiperspective_perceptron.cc42 #include "debug/Branch.hh"
235 DPRINTF(Branch, "%d bits of metadata so far, %d left out of "
237 DPRINTF(Branch, "table size is %d bits, %d entries for 5 bit, %d entries "
241 DPRINTF(Branch, "%d total bits (%0.2fKB)\n", totalbits,
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ui/
H A Dbeq.S17 # Branch tests
H A Dbge.S17 # Branch tests
H A Dblt.S17 # Branch tests
H A Dbne.S17 # Branch tests
H A Dbgeu.S17 # Branch tests
H A Dbltu.S17 # Branch tests
/gem5/src/cpu/minor/
H A Dfetch2.cc48 #include "debug/Branch.hh"
153 DPRINTF(Branch, "Unpredicted branch seen inst: %s\n", *inst);
163 DPRINTF(Branch, "Branch predicted correctly inst: %s\n", *inst);
169 DPRINTF(Branch, "Branch mis-predicted inst: %s\n", *inst);
179 DPRINTF(Branch, "Branch mis-predicted target inst: %s target: %s\n",
202 DPRINTF(Branch, "Trying to predict for inst: %s\n", *inst);
213 DPRINTF(Branch, "No
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H A Dexecute.cc51 #include "debug/Branch.hh"
231 DPRINTF(Branch, "tryToBranch before: %s after: %s%s\n",
247 DPRINTF(Branch, "Advancing current PC from: %s to: %s\n",
256 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x but"
262 /* Branch prediction got the right target, kill the branch and
266 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x correctly"
272 /* Branch prediction got the wrong target */
273 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x"
282 DPRINTF(Branch, "Unpredicted branch from 0x%x to 0x%x inst: %s\n",
316 DPRINTF(Branch, "Branc
[all...]
/gem5/src/arch/hsail/insts/
H A Dbranch.hh62 setFlag(Branch);
178 setFlag(Branch);
346 setFlag(Branch);
/gem5/src/gpu-compute/
H A Dgpu_static_inst.hh96 bool isBranch() const { return _flags[Branch]; }
/gem5/util/minorview/
H A Dmodel.py177 class Branch(BlobVisualData): class in inherits:BlobVisualData
178 """Branch data new stream and prediction sequence numbers, a branch
198 # self.branch = special_view_decoder(Branch)(branch)
200 print "Bad Branch data:", string
400 'branch': Branch,
/gem5/src/cpu/o3/
H A Dfetch_impl.hh578 DPRINTF(Fetch, "[tid:%i] [sn:%llu] Branch at PC %#x "
582 DPRINTF(Fetch, "[tid:%i] [sn:%llu] Branch at PC %#x "
587 DPRINTF(Fetch, "[tid:%i] [sn:%llu] Branch at PC %#x "
1354 DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC);
1462 case FetchPolicy::Branch:
1593 panic("Branch Count Fetch policy unimplemented\n");

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