/gem5/util/systemc/gem5_within_systemc/ |
H A D | sc_gem5_control.hh | 58 #include <vector> 111 const std::vector<std::string> ¶m_values);
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/gem5/src/mem/qos/ |
H A D | mem_sink.hh | 184 std::vector<PacketQueue> readQueue; 189 std::vector<PacketQueue> writeQueue;
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/gem5/src/arch/arm/ |
H A D | semihosting.cc | 90 const std::vector<const char *> ArmSemihosting::fmodes{ 119 const std::vector<uint8_t> ArmSemihosting::features{ 172 std::vector<uint64_t> argv(call->argc64 + 1); 207 std::vector<uint64_t> argv(call->argc32 + 1); 272 std::vector<char> buf(len + 1); 282 std::vector<uint64_t> &argv) 310 std::vector<uint64_t> &argv) 333 std::vector<uint64_t> &argv) 345 std::vector<uint64_t> &argv) 362 std::vector<uint64_ [all...] |
/gem5/src/arch/riscv/ |
H A D | stacktrace.hh | 62 std::vector<Addr> stack; 93 const std::vector<Addr> &
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/gem5/src/arch/power/ |
H A D | stacktrace.hh | 62 std::vector<Addr> stack; 93 const std::vector<Addr> &
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/gem5/src/cpu/testers/directedtest/ |
H A D | RubyDirectedTester.hh | 35 #include <vector> 101 std::vector<MasterPort*> ports;
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/gem5/src/cpu/pred/ |
H A D | tage_base.hh | 54 #include <vector> 429 std::vector<unsigned> tagTableTagWidths; 430 std::vector<int> logTagTableSizes; 432 std::vector<bool> btablePrediction; 433 std::vector<bool> btableHysteresis; 445 // @TODO Convert to std::vector<bool> 459 std::vector<ThreadHistory> threadHistory; 470 std::vector<int8_t> useAltPredForNewlyAllocated; 481 std::vector<bool> noSkip;
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/gem5/src/sim/ |
H A D | sim_object.hh | 53 #include <vector> 100 typedef std::vector<SimObject *> SimObjectList;
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H A D | process.hh | 41 #include <vector> 166 std::vector<ContextID> contextIds; 185 std::vector<std::string> argv; 186 std::vector<std::string> envp; 243 std::vector<EmulatedDriver *> drivers;
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H A D | serialize.hh | 60 #include <vector> 411 const std::vector<T> ¶m) 413 typename std::vector<T>::size_type size = param.size(); 417 for (typename std::vector<T>::size_type i = 1; i < size; ++i) { 500 std::vector<std::string> tokens; 504 // Need this if we were doing a vector 511 for (std::vector<std::string>::size_type i = 0; i < tokens.size(); i++) { 512 // need to parse into local variable to handle vector<bool>, 515 // vector) 526 // assign parsed value to vector [all...] |
/gem5/src/base/filters/ |
H A D | base.hh | 35 #include <vector> 52 std::vector<SatCounter> filter;
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/gem5/src/dev/x86/ |
H A D | i82094aa.hh | 64 Bitfield<7, 0> vector; member in class:X86ISA::I82094AA 85 std::vector<IntSinkPin<I82094AA> *> inputs;
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H A D | i8259.hh | 51 std::vector<IntSourcePin<I8259> *> output; 52 std::vector<IntSinkPin<I8259> *> inputs; 63 // The higher order bits of the vector to return 67 // A bit vector of lines with slaves attached, or the slave id, depending
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/gem5/ext/googletest/googlemock/test/ |
H A D | gmock-generated-matchers_test.cc | 42 #include <vector> 55 using std::vector; 289 Matcher<const vector<int>&> m = ElementsAre(); 294 Matcher<vector<int> > m = ElementsAre(Gt(5)); 306 Matcher<vector<int> > m = ElementsAre(); 333 Matcher<const vector<int>& > m = 337 vector<int> test_vector(a, a + GTEST_ARRAY_SIZE_(a)); 355 Matcher<const vector<int>& > m = ElementsAre(1, GreaterThan(5)); 357 vector<int> v; 368 vector<strin [all...] |
/gem5/ext/pybind11/tests/ |
H A D | pybind11_cross_module_tests.cpp | 89 py::bind_vector<std::vector<int>>(m, "VectorInt"); 91 m.def("load_vector_via_binding", [](std::vector<int> &v) { 113 // We can't test both stl.h and stl_bind.h conversions of `std::vector<bool>` within 116 py::bind_vector<std::vector<bool>>(m, "VectorBool"); 121 m.def("missing_header_arg", [](std::vector<float>) { }); 122 m.def("missing_header_return", []() { return std::vector<float>(); });
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/gem5/src/base/ |
H A D | circlebuf.hh | 45 #include <vector> 52 * Circular buffer backed by a vector though a CircularQueue. 55 * vector. 179 std::vector<T> temp(param.size()); 189 std::vector<T> temp; 201 std::vector<T> temp(param.size()); 211 std::vector<T> temp;
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H A D | coroutine.test.cc | 89 const std::vector<int> input{ 1, 2, 3 }; 90 const std::vector<int> expected_values = input; 119 const std::vector<int> output{ 1, 2, 3 }; 120 const std::vector<int> expected_values = output; 148 const std::vector<int> expected_values{
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/gem5/src/arch/x86/ |
H A D | interrupts.cc | 225 X86ISA::Interrupts::requestInterrupt(uint8_t vector, argument 238 if (vector > IRRV) 239 IRRV = vector; 240 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) { 241 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector); 243 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 245 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 253 smiVector = vector; 256 nmiVector = vector; 259 extIntVector = vector; [all...] |
/gem5/src/systemc/tests/systemc/compliance_1666/test203a/ |
H A D | test203a.cpp | 19 std::vector<sc_object*> children = h.get_child_objects();
61 std::vector<sc_object*> children = this->get_child_objects();
74 std::vector<sc_object*> children2 = h2.get_child_objects();
90 std::vector<sc_object*> children3 = h3.get_child_objects();
120 std::vector<sc_object*> children3 = h3.get_child_objects();
144 std::vector<sc_object*> children3 = h3.get_child_objects();
168 std::vector<sc_object*> children3 = h3.get_child_objects();
190 std::vector<sc_object*> children3 = h3.get_child_objects();
212 std::vector<sc_object*> children2 = h2.get_child_objects();
231 std::vector<sc_objec [all...] |
/gem5/ext/dsent/model/electrical/router/ |
H A D | RouterInputPort.cc | 25 #include <vector> 37 using std::vector; 75 const vector<unsigned int>& number_vcs_per_vn_vector = castStringVector<unsigned int>(getParameter("NumberVirtualChannelsPerVirtualNetwork").split("[,]")); 76 const vector<unsigned int>& number_bufs_per_vc_vector = castStringVector<unsigned int>(getParameter("NumberBuffersPerVirtualChannel").split("[,]")); 136 vector<String> rd_addr_dff_names(number_addr_bits, ""); 137 vector<StdCell*> rd_addr_dffs(number_addr_bits, NULL); 192 vector<ElectricalModel*> rd_addr_dffs(number_addr_bits, NULL);
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/gem5/src/gpu-compute/ |
H A D | wavefront.hh | 43 #include <vector> 180 // map virtual to physical vector register 192 std::vector<Addr> lastAddr; 193 std::vector<uint32_t> workItemId[3]; 194 std::vector<uint32_t> workItemFlatId; 229 // number of vector registers reserved by WF 236 std::vector<uint32_t> oldVgpr; 243 std::vector<uint64_t> oldDgpr; 253 std::vector<int> barCnt; 266 // The vector widt [all...] |
/gem5/src/mem/ |
H A D | coherent_xbar.hh | 78 * Declare the layers of this crossbar, one vector for requests, 81 std::vector<ReqLayer*> reqLayers; 82 std::vector<RespLayer*> respLayers; 83 std::vector<SnoopRespLayer*> snoopLayers; 253 std::vector<SnoopRespPort*> snoopRespPorts; 255 std::vector<QueuedSlavePort*> snoopPorts; 332 const std::vector<QueuedSlavePort*>& dests); 370 const std::vector<QueuedSlavePort*>&
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/gem5/ext/dsent/model/electrical/ |
H A D | DFFRAM.cc | 114 vector<String> dff_names(number_entries, ""); 115 vector<StdCell*> dffs(number_entries, NULL); 144 vector<String> nand2cg1_names(number_entries, ""); 145 vector<StdCell*> nand2cg1s(number_entries, NULL); 146 vector<String> invcg1_names(number_entries, ""); 147 vector<StdCell*> invcg1s(number_entries, NULL); 301 vector<ElectricalModel*> nand2cg1s(number_entries, NULL); 302 vector<ElectricalModel*> invcg1s(number_entries, NULL); 316 vector<ElectricalModel*> dffs(number_entries, NULL);
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/gem5/src/cpu/ |
H A D | timing_expr.hh | 83 std::vector<uint64_t> results; 84 std::vector<bool > resultAvailable; 142 std::vector<TimingExpr *> defns;
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/gem5/ext/dsent/model/optical_graph/ |
H A D | OpticalWavelength.cc | 41 m_data_paths_ = new vector<OpticalDataPath>; 90 const vector<OpticalDataPath>* OpticalWavelength::getDataPaths() const 92 return (const vector<OpticalDataPath>*) m_data_paths_;
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