Searched refs:set (Results 276 - 300 of 322) sorted by relevance

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/gem5/src/sim/
H A Dsystem.hh625 /** Process set to track which PIDs have already been allocated */
626 std::set<int> PIDs;
/gem5/tests/testing/
H A Dtests.py297 ref_files = set(self.ref_files())
/gem5/src/mem/slicc/symbols/
H A DStateMachine.py63 # the members in self.objects form the entire set of data members.
91 # form the entire set of data members of the machine.
95 self.debug_flags = set()
283 seen_types = set()
486 seen_types = set()
571 # set for maintaining the vnet, direction pairs already seen for this
574 vnet_dir_set = set()
593 m_net_ptr->set${network}NetQueue(m_version + base, $vid->getOrdered(), $vnet,
1313 # Only set next_state if it changes
/gem5/src/python/m5/
H A Dsimulate.py267 old_cpu_set = set(old_cpus)
/gem5/src/base/
H A Dstatistics.hh57 * specific set of stats
220 * Check that this stat has been set up properly and is ready for
266 info->flags.set(display);
283 info->flags.set(display);
338 this->info()->flags.set(_flags);
516 void set(Counter val) { data = val; }
584 * set values.
588 set(Counter val)
596 * Increment the current count by the provided value, calls set.
599 void inc(Counter val) { set(curren
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H A Dstatistics.cc114 info()->flags.set(init);
/gem5/src/cpu/minor/
H A Dfetch1.cc83 DPRINTF(Fetch, "lineSnap set to cache line size of: %d\n",
89 DPRINTF(Fetch, "maxLineWidth set to cache line size of: %d\n",
204 thread.pc.set(aligned_pc + request_size + pc_low_bits);
206 thread.pc.set(aligned_pc + request_size);
533 * actually set the prediction to an *older* value if new
608 * if we're still processing the same stream (as set by streamSeqNum)
/gem5/ext/googletest/googletest/include/gtest/internal/
H A Dgtest-param-util.h40 #include <set>
565 std::set<std::string> test_param_names;
H A Dgtest-port.h325 // probably other compilers set that too in C++11 mode.
1752 // Maps a thread to a set of ThreadLocals that have values instantiated on that
1824 // tl.set(150); // Changes the value for thread 2 only.
1829 // tl.set(200);
1857 void set(const T& value) { *pointer() = value; } function in class:testing::internal::ThreadLocal
2050 void set(const T& value) { *pointer() = value; } function in class:testing::internal::ThreadLocal
2169 void set(const T& value) { value_ = value; } function in class:testing::internal::ThreadLocal
2393 // Environment variables which we programmatically clear will be set to the
/gem5/src/arch/x86/
H A Dpagetable_walker.cc522 flags.set(Request::UNCACHEABLE, uncacheable);
590 flags.set(Request::UNCACHEABLE);
/gem5/src/arch/arm/
H A Dutility.cc135 newPC.set(tc->readIntReg(INTREG_X30));
137 newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
183 // setMiscReg "with effect" will set the misc register mapping correctly.
H A Dtable_walker.cc536 flag.set(Request::UNCACHEABLE);
540 flag.set(Request::SECURE);
568 flag.set(Request::SECURE);
703 flag.set(Request::UNCACHEABLE);
998 flag.set(Request::UNCACHEABLE);
1002 flag.set(Request::SECURE);
1498 * enabled if set, do l1.Desc.setAp0() instead of generating
1537 flag.set(Request::SECURE);
1702 flag.set(Request::SECURE);
1773 * if set, d
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/gem5/src/dev/arm/
H A Dgic_v3_redistributor.cc510 "pending bit set\n", int_id);
550 "int_id %d active set\n", int_id);
711 "int_id %d (PPI) pending bit set\n", int_id);
748 "int_id %d (SGI) pending bit set\n", int_id);
892 Gicv3Redistributor::setClrLPI(uint64_t data, bool set)
915 if (set) {
/gem5/tests/gem5/
H A Dfixture.py195 targets = set(self.required_by)
/gem5/src/cpu/trace/
H A Dtrace_cpu.hh48 #include <set>
115 * sequential container, std::set to std::vector. We only check head of the
491 * Returns the traceComplete variable which is set when end of the
494 * @return bool true if traceComplete is set, false otherwise.
609 /** The address space id which is set if the virtual address is set */
632 * of source registers used to set maximum size of the array
806 * clock domain frequency must also be set to match the expected
888 * @param trace_offset trace offset set by comparing both traces
914 * @param num_dep the number of dependencies set i
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/gem5/ext/googletest/googletest/test/
H A Dgtest-printers_test.cc45 #include <set>
202 using ::std::set;
910 set<unsigned int> set1(a, a + 3);
/gem5/src/cpu/o3/
H A Dcommit_impl.hh48 #include <set>
121 pc[tid].set(0);
385 pc[tid].set(0);
635 // microcode unless this is set.
H A Dlsq_unit_impl.hh307 loadQueue.back().set(load_inst);
330 storeQueue.back().set(store_inst);
640 // Store conditionals and Atomics need to set themselves as able to
/gem5/ext/systemc/src/sysc/utils/
H A Dsc_string.cpp359 sc_string_old::set( int i, char c ) function in class:sc_dt::sc_string_old
/gem5/configs/common/
H A DHMC.py289 cache line size will be set to this value.\nDefault:\
351 # set the clock frequency for serial link
/gem5/ext/testlib/
H A Dhandlers.py441 self._shutdown.set()
/gem5/src/arch/arm/kvm/
H A Darmv8_cpu.cc116 const std::set<MiscRegIndex> ArmV8KvmCPU::deviceRegSet = {
H A Darm_cpu.cc190 const std::set<uint64_t> ArmKvmCPU::invariant_regs(
326 // Just set the return value using the KVM API instead of messing
748 pc.set(getOneRegU32(REG_CORE32(usr_regs.ARM_pc)));
/gem5/src/python/m5/ext/pyfdt/
H A Dpyfdt.py562 curnames = set([subnode.get_name() for subnode in self.subdata
564 cmpnames = set([subnode.get_name() for subnode in node
644 Returns set with (path string, node object)
1039 Returns a set with the pre-node Nops, the Root Node,
/gem5/util/minorview/
H A Dview.py228 self.view.dataSelect.ids = set("SPLFE")

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