Searched refs:sc_signal (Results 576 - 600 of 1041) sorted by relevance

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/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/
H A Dstimulus.h47 sc_signal<bool>& reset;
52 sc_signal<bool>& input_valid;
56 sc_signal<bool>& RESET,
61 sc_signal<bool>& INPUT_VALID
/gem5/src/systemc/tests/systemc/misc/gnats/pr-130/
H A Dpr-130.cpp46 const sc_signal<bool>& x;
50 const sc_signal<bool>& X )
65 const sc_signal<bool>& x;
69 const sc_signal<bool>& X )
/gem5/src/systemc/tests/systemc/misc/sim_tests/biquad/biquad3/
H A Dmain.cpp49 sc_signal<float> sample;
50 sc_signal<float> result;
51 sc_signal<bool> reset;
52 sc_signal<float> delayed_out;
/gem5/src/systemc/tests/systemc/misc/sim_tests/cycle_dw8051_demo/
H A Dmain.cpp119 sc_signal<bool> mem_wr_n("mem_wr_n"); // write strobe
120 sc_signal<bool> mem_rd_n("mem_rd_n"); // read enable sampled
121 sc_signal<bool> mem_pswr_n("mem_pswr_n"); // write enable (ROM)
122 sc_signal<bool> mem_psrd_n("mem_psrd_n"); // read enable (ROM)
123 sc_signal<bool> mem_ale("mem_ale"); // ext latch enable
124 sc_signal<bool> mem_ea_n("mem_ea_n"); // ext prog mem enable
126 // sc_signal<bool> port_pin_reg_n(); // select read from ext reg or pin
127 sc_signal<bool> p0_mem_reg_n("p0_mem_reg_n"); // select port reg
128 sc_signal<bool> p0_addr_data_n("p0_addr_data_n");// select data
129 sc_signal<boo
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/gem5/src/systemc/tests/systemc/misc/sim_tests/srlatch/
H A Dtestbench.h57 sc_signal<bool>& Q,
58 sc_signal<bool>& QP,
59 sc_signal<bool>& S,
60 sc_signal<bool>& R )
/gem5/src/systemc/tests/systemc/misc/synth/add_chain/
H A Ddata_gen.h51 const sc_signal<bool>& ready;
53 sc_signal<int>& addr;
58 const sc_signal<bool>& READY,
60 sc_signal<int>& ADDR )
/gem5/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/
H A Dreset_stim.cpp53 sc_signal<bool>& ready;
54 sc_signal<bool>& reset;
55 sc_signal<int>& addr;
60 sc_signal<bool>& READY,
61 sc_signal<bool>& RESET,
62 sc_signal<int>& ADDR )
116 sc_signal<bool>& READY,
117 sc_signal<bool>& RESET,
118 sc_signal<int>& ADDR )
/gem5/src/systemc/tests/systemc/misc/unit/structure/clocks/
H A Dtb.h44 sc_signal<bool> out_clk_pos;
45 sc_signal<bool> out_clk_neg;
46 sc_signal<bool> out_clk2_pos;
47 sc_signal<bool> out_clk2_neg;
/gem5/src/systemc/tests/systemc/misc/user_guide/chpt12.1/
H A Daccessor.h50 sc_signal<bool>& chip_select; //output
51 sc_signal<bool>& write_enable; //output
59 sc_signal<bool>& CHIP_SELECT,
60 sc_signal<bool>& WRITE_ENABLE,
H A Dram.h48 const sc_signal<bool>& cs; //input
49 const sc_signal<bool>& we; //input
56 const sc_signal<bool>& CS,
57 const sc_signal<bool>& WE,
/gem5/src/systemc/tests/systemc/misc/user_guide/chpt12.2/
H A Daccessor.h50 sc_signal<bool>& chip_select; //output
51 sc_signal<bool>& write_enable; //output
62 sc_signal<bool>& CHIP_SELECT,
63 sc_signal<bool>& WRITE_ENABLE,
H A Dram.h50 const sc_signal<bool>& cs; //input
51 const sc_signal<bool>& we; //input
65 const sc_signal<bool>& CS,
66 const sc_signal<bool>& WE,
/gem5/src/systemc/tests/systemc/misc/user_guide/chpt4.3/
H A Dtb.h44 sc_signal<bool> out_clk_pos;
45 sc_signal<bool> out_clk_neg;
46 sc_signal<bool> out_clk2_pos;
47 sc_signal<bool> out_clk2_neg;
/gem5/src/systemc/tests/systemc/misc/v1.0/dash1/
H A Dmain.cpp85 sc_signal<bool> speed_pulses("speed_pulses");
86 sc_signal<bool> dist_pulses("dist_pulses");
88 sc_signal<bool> reset("reset");
89 sc_signal<int> speed("speed");
90 sc_signal<bool> start("start");
93 sc_signal<double> disp_speed("disp_speed");
94 sc_signal<double> disp_angle("disp_angle");
95 sc_signal<double> disp_total_dist("disp_total_dist");
96 sc_signal<double> disp_partial_dist("disp_partial_dist");
/gem5/src/systemc/tests/systemc/tracing/wif_trace/pct1/
H A Dmain.cpp45 sc_signal<bool> tx;
46 sc_signal<bool> wr;
47 sc_signal<int> dout;
48 sc_signal<bool> two_stop_bits;
/gem5/src/systemc/tests/systemc/misc/sim_tests/manual_clock/
H A Dmanual_clock.cpp55 sc_signal<bool>& A,
56 sc_signal<bool>& B,
57 sc_signal<bool>& C )
93 sc_signal<bool>& A,
94 sc_signal<bool>& B,
95 sc_signal<bool>& C )
130 sc_signal<bool>& A,
131 sc_signal<bool>& B,
132 sc_signal<bool>& C,
133 sc_signal<boo
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/gem5/src/systemc/tests/systemc/misc/user_guide/newsched/test1/
H A Dtest1.cpp54 const sc_signal<int>& in1;
55 const sc_signal<int>& in2;
56 sc_signal<int>& out;
60 const sc_signal<int>& IN1,
61 const sc_signal<int>& IN2,
62 sc_signal<int>& OUT_)
90 const sc_signal<int>& in;
91 sc_signal<int>& out;
95 const sc_signal<int>& IN_,
96 sc_signal<in
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/gem5/src/systemc/tests/systemc/misc/user_guide/newsched/test2/
H A Dtest2.cpp53 const sc_signal<int>& in1;
54 const sc_signal<int>& in2;
55 sc_signal<int>& out;
59 const sc_signal<int>& IN1,
60 const sc_signal<int>& IN2,
61 sc_signal<int>& OUT_)
89 const sc_signal<int>& in;
90 sc_signal<int>& out;
94 const sc_signal<int>& IN_,
95 sc_signal<in
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/gem5/src/systemc/tests/systemc/misc/user_guide/newsched/test8/
H A Dtest8.cpp59 sc_signal<int>& out;
65 sc_signal<int>& OUT_)
87 const sc_signal<int>& in1;
88 const sc_signal<int>& in2;
89 const sc_signal<int>& in3;
90 const sc_signal<int>& in4;
95 const sc_signal<int>& IN1,
96 const sc_signal<int>& IN2,
97 const sc_signal<int>& IN3,
98 const sc_signal<in
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/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/
H A Ddatatypes.h53 const sc_signal<bool>& reset ;
58 const sc_signal<bool>& in_valid; // Input port
63 sc_signal<bool>& out_ack; // Output port
64 sc_signal<bool>& out_valid; // Output port
74 const sc_signal<bool>& RESET,
79 const sc_signal<bool>& IN_VALID, // Input port
84 sc_signal<bool>& OUT_ACK,
85 sc_signal<bool>& OUT_VALID // Output port
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/
H A Dbitwidth.h53 const sc_signal<bool>& reset ;
58 const sc_signal<bool>& in_valid; // Input port
63 sc_signal<bool>& out_ack; // Output port
64 sc_signal<bool>& out_valid; // Output port
74 const sc_signal<bool>& RESET,
79 const sc_signal<bool>& IN_VALID, // Input port
84 sc_signal<bool>& OUT_ACK,
85 sc_signal<bool>& OUT_VALID // Output port
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/
H A Dsharing.h47 const sc_signal<bool>& reset ;
53 const sc_signal<bool>& in_valid; // Input port
54 sc_signal<bool>& out_ack; // Output port
60 sc_signal<bool>& out_valid; // Output port
69 const sc_signal<bool>& RESET,
75 const sc_signal<bool>& IN_VALID, // Input port
76 sc_signal<bool>& OUT_ACK,
82 sc_signal<bool>& OUT_VALID // Output port
/gem5/src/systemc/tests/systemc/misc/communication/signals/bool/
H A Dmain.cpp44 sc_signal<bool> ack;
45 sc_signal<bool> ready;
H A Dproc1.h53 sc_signal<bool>& READY,
54 sc_signal<bool>& ACK )
H A Dproc2.h53 sc_signal<bool>& READY,
54 sc_signal<bool>& ACK )

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