Searched refs:sc_signal (Results 501 - 525 of 1041) sorted by relevance

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/gem5/src/systemc/tests/systemc/misc/user_guide/chpt14.1/
H A Dmain.cpp45 sc_signal<bool> data_ready;
46 sc_signal<bool> data_ack;
47 sc_signal<int> data;
/gem5/src/systemc/tests/systemc/misc/user_guide/chpt3.2/
H A Dmain.cpp46 sc_signal<bool> handshake ("HS");
47 sc_signal<bool> found;
48 sc_signal<char> stream ("ST");
/gem5/src/systemc/tests/systemc/misc/user_guide/chpt4.2/
H A Dmain.cpp51 sc_signal<double> in1;
52 sc_signal<double> in2;
53 sc_signal<double> powr;
H A Dtestbench.h50 const sc_signal<double>& IN_,
51 sc_signal<double>& OUT1,
52 sc_signal<double>& OUT2)
/gem5/src/systemc/tests/systemc/misc/user_guide/chpt4.4/
H A Dmain.cpp47 sc_signal<double> in1;
48 sc_signal<double> in2;
49 sc_signal<double> powr;
H A Dtestbench.h50 const sc_signal<double>& IN_,
51 sc_signal<double>& OUT1,
52 sc_signal<double>& OUT2)
/gem5/src/systemc/tests/systemc/misc/user_guide/chpt5.1/
H A Dmain.cpp46 sc_signal<int> number;
47 sc_signal<int> resulta;
48 sc_signal<int> resultm;
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/
H A Dmain.cpp44 sc_signal<bool> reset;
45 sc_signal<int> stimulus_line1;
47 sc_signal<bool> input_valid;
48 sc_signal<bool> output_valid;
49 sc_signal<int> result_line1;
/gem5/src/systemc/tests/systemc/misc/user_guide/chpt10.1/
H A Dmain.cpp49 sc_signal<bool> reset;
52 sc_signal<bool> cin;
53 sc_signal<bool> ready;
55 sc_signal<bool> co;
56 sc_signal<bool> done;
/gem5/src/systemc/tests/systemc/misc/user_guide/chpt11.3/
H A Dmean.h43 typedef sc_signal<sc_bv<24> > signal_bool_vector;
53 const sc_signal<bool>& data_available; //input
54 sc_signal<bool>& data_ready; //output
61 const sc_signal<bool>& DATA_AVAILABLE,
62 sc_signal<bool>& DATA_READY)
/gem5/src/systemc/tests/systemc/misc/user_guide/chpt11.4/
H A Dmean.h43 typedef sc_signal<sc_bv<24> > sc_signal_bool_vector;
53 const sc_signal<bool>& receiver_ready; //input
54 sc_signal<bool>& send_input; //output
61 const sc_signal<bool>& RECEIVER_READY,
62 sc_signal<bool>& SEND_INPUT)
/gem5/src/systemc/tests/systemc/misc/user_guide/param_model/
H A Dmain.cpp54 sc_signal<bool> reset;
57 sc_signal<bool> cin;
58 sc_signal<bool> ready;
60 sc_signal<bool> co;
61 sc_signal<bool> done;
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/
H A Dmain.cpp45 sc_signal<bool> reset;
46 sc_signal<int> stimulus_line1;
47 sc_signal<unsigned int> stimulus_line2;
51 sc_signal<bool> input_valid;
52 sc_signal<bool> output_valid;
53 sc_signal<int> result_line1;
54 sc_signal<unsigned int> result_line2;
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/
H A Dmain.cpp45 sc_signal<bool> reset;
46 sc_signal<int> stimulus_line1;
47 sc_signal<unsigned int> stimulus_line2;
51 sc_signal<bool> input_valid;
52 sc_signal<bool> output_valid;
53 sc_signal<int> result_line1;
54 sc_signal<unsigned int> result_line2;
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/
H A Dmain.cpp45 sc_signal<bool> reset;
46 sc_signal<int> stimulus_line1;
47 sc_signal<unsigned int> stimulus_line2;
51 sc_signal<bool> input_valid;
52 sc_signal<bool> output_valid;
53 sc_signal<int> result_line1;
54 sc_signal<unsigned int> result_line2;
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/
H A Dmain.cpp45 sc_signal<bool> reset;
46 sc_signal<int> stimulus_line1;
47 sc_signal<unsigned int> stimulus_line2;
51 sc_signal<bool> input_valid;
52 sc_signal<bool> output_valid;
53 sc_signal<int> result_line1;
54 sc_signal<unsigned int> result_line2;
/gem5/src/systemc/tests/systemc/misc/parsing/T_1_1_2_6/
H A DT_1_1_2_6.cpp46 const sc_signal<bool>& input;
47 sc_signal<bool>& output;
51 const sc_signal<bool>& INPUT,
52 sc_signal<bool>& OUTPUT )
64 sc_signal<bool> sig;
70 const sc_signal<bool>& input,
71 sc_signal<bool>& output )
/gem5/src/systemc/tests/systemc/misc/stars/star110069/
H A Dmem0.h38 typedef sc_signal<sc_bv<8> > sc_signal_bool_vector;
53 const sc_signal<bool>& reset ;
56 const sc_signal<bool>& in_valid; // Input port
59 sc_signal<bool>& out_valid; // Output port
70 const sc_signal<bool>& RESET,
73 const sc_signal<bool>& IN_VALID, // Input port
76 sc_signal<bool>& OUT_VALID, // Output port
/gem5/src/systemc/tests/systemc/misc/sim_tests/cycle_dw8051_demo/
H A Dcycle_model.h160 sc_signal<bool>& mem_wr_n;
161 sc_signal<bool>& mem_rd_n;
162 sc_signal<bool>& mem_pswr_n;
163 sc_signal<bool>& mem_psrd_n;
164 sc_signal<bool>& mem_ale;
165 const sc_signal<bool>& mem_ea_n;
167 sc_signal<bool>& p0_mem_reg_n;
168 sc_signal<bool>& p0_addr_data_n;
169 sc_signal<bool>& p2_mem_reg_n;
194 sc_signal<boo
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/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/
H A Daddition.h52 const sc_signal<bool>& reset ;
53 const sc_signal<int>& in_value1;
58 const sc_signal<bool>& in_valid; // Input port
59 sc_signal<int>& out_value1; // Output port
64 sc_signal<bool>& out_valid;
73 const sc_signal<bool>& RESET,
74 const sc_signal<int>& IN_VALUE1,
79 const sc_signal<bool>& IN_VALID, // Input port
80 sc_signal<int>& OUT_VALUE1,
85 sc_signal<boo
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/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/
H A Ddivide.h47 const sc_signal<bool>& reset ;
48 const sc_signal<int>& in_value1; // Input port
53 const sc_signal<bool>& in_valid; // Input port
54 sc_signal<int>& out_value1; // Output port
59 sc_signal<bool>& out_valid; // Output port
68 const sc_signal<bool>& RESET,
69 const sc_signal<int>& IN_VALUE1,
74 const sc_signal<bool>& IN_VALID, // Input port
75 sc_signal<int>& OUT_VALUE1,
80 sc_signal<boo
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/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/
H A Dmodulo.h53 const sc_signal<bool>& reset ;
54 const sc_signal<int>& in_value1; // Input port
59 const sc_signal<bool>& in_valid; // Input port
60 sc_signal<int>& out_value1; // Output port
65 sc_signal<bool>& out_valid; // Output port
74 const sc_signal<bool>& RESET,
75 const sc_signal<int>& IN_VALUE1,
80 const sc_signal<bool>& IN_VALID, // Input port
81 sc_signal<int>& OUT_VALUE1,
86 sc_signal<boo
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/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/
H A Dmult.h53 const sc_signal<bool>& reset ;
54 const sc_signal<int>& in_value1; // Input port
59 const sc_signal<bool>& in_valid; // Input port
60 sc_signal<int>& out_value1; // Output port
65 sc_signal<bool>& out_valid; // Output port
74 const sc_signal<bool>& RESET,
75 const sc_signal<int>& IN_VALUE1,
80 const sc_signal<bool>& IN_VALID, // Input port
81 sc_signal<int>& OUT_VALUE1,
86 sc_signal<boo
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/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/
H A Dsubtract.h47 const sc_signal<bool>& reset ;
48 const sc_signal<int>& in_value1; // Input port
53 const sc_signal<bool>& in_valid; // Input port
54 sc_signal<int>& out_value1; // Output port
59 sc_signal<bool>& out_valid; // Output port
68 const sc_signal<bool>& RESET,
69 const sc_signal<int>& IN_VALUE1,
74 const sc_signal<bool>& IN_VALID, // Input port
75 sc_signal<int>& OUT_VALUE1,
80 sc_signal<boo
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/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/
H A Dbalancing.h47 const sc_signal<bool>& reset ;
51 const sc_signal<bool>& in_valid;
55 sc_signal<bool>& out_valid1;
56 sc_signal<bool>& out_valid2;
57 sc_signal<bool>& out_valid3;
66 const sc_signal<bool>& RESET,
70 const sc_signal<bool>& IN_VALID,
74 sc_signal<bool>& OUT_VALID1,
75 sc_signal<bool>& OUT_VALID2,
76 sc_signal<boo
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