/gem5/src/arch/arm/tracers/ |
H A D | tarmac_record.hh | 101 const std::string &prefix = "") const override; member in struct:Trace::TarmacTracerRecord::TraceInstEntry 136 const std::string &prefix = "") const override; member in struct:Trace::TarmacTracerRecord::TraceRegEntry 172 const std::string &prefix = "") const override; member in struct:Trace::TarmacTracerRecord::TraceMemEntry 185 virtual void dump() override; member in class:Trace::TarmacTracerRecord
|
/gem5/src/mem/cache/compressors/ |
H A D | base.hh | 156 void regStats() override; member in class:BaseCacheCompressor
|
/gem5/src/mem/cache/tags/ |
H A D | super_blk.hh | 120 std::string print() const override; member in class:CompressionBlk
|
/gem5/src/mem/ |
H A D | comm_monitor.hh | 82 void init() override; member in class:CommMonitor 83 void startup() override; member in class:CommMonitor 84 void regProbePoints() override; member in class:CommMonitor 88 PortID idx=InvalidPortID) override; member in class:CommMonitor
|
H A D | backdoor.hh | 57 void process() override { cbFunction(_backdoor); } 60 void autoDestruct() override { delete this; }
|
H A D | bridge.hh | 321 PortID idx=InvalidPortID) override; member in class:Bridge 323 void init() override; member in class:Bridge
|
H A D | page_table.hh | 161 void serialize(CheckpointOut &cp) const override; member in class:EmulationPageTable 162 void unserialize(CheckpointIn &cp) override; member in class:EmulationPageTable
|
H A D | multi_level_page_table.hh | 205 initState() override 216 map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags = 0) override 236 remap(Addr vaddr, int64_t size, Addr new_vaddr) override 259 unmap(Addr vaddr, int64_t size) override 277 serialize(CheckpointOut &cp) const override 288 unserialize(CheckpointIn &cp) override
|
/gem5/src/sim/ |
H A D | dvfs_handler.hh | 177 void serialize(CheckpointOut &cp) const override; member in class:DVFSHandler 178 void unserialize(CheckpointIn &cp) override; member in class:DVFSHandler
|
/gem5/src/arch/arm/insts/ |
H A D | pred_inst.hh | 254 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::PredImmOp 275 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::PredIntOp 294 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::DataImmOp 313 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::DataRegOp 331 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::DataRegRegOp 362 fetchMicroop(MicroPC microPC) const override 369 execute(ExecContext *, Trace::InstRecord *) const override 375 Addr pc, const SymbolTable *symtab) const override;
|
/gem5/src/cpu/testers/rubytest/ |
H A D | RubyTester.hh | 99 PortID idx=InvalidPortID) override; member in class:RubyTester 107 void init() override; member in class:RubyTester
|
/gem5/src/cpu/ |
H A D | thread_state.hh | 66 void serialize(CheckpointOut &cp) const override; member in struct:ThreadState 68 void unserialize(CheckpointIn &cp) override; member in struct:ThreadState
|
/gem5/src/mem/cache/prefetch/ |
H A D | spatio_temporal_memory_streaming.hh | 93 void reset() override 194 std::vector<AddrPriority> &addresses) override; member in class:STeMSPrefetcher
|
/gem5/src/mem/cache/ |
H A D | mshr.hh | 355 bool sendPacket(BaseCache &cache) override; 474 QueueEntry::Target *getTarget() override 526 const std::string &prefix = "") const override; 535 bool matchBlockAddr(const Addr addr, const bool is_secure) const override; 536 bool matchBlockAddr(const PacketPtr pkt) const override; 537 bool conflictAddr(const QueueEntry* entry) const override;
|
H A D | base.hh | 293 virtual bool recvTimingSnoopResp(PacketPtr pkt) override; member in class:BaseCache::CpuSidePort 295 virtual bool tryTiming(PacketPtr pkt) override; member in class:BaseCache::CpuSidePort 297 virtual bool recvTimingReq(PacketPtr pkt) override; member in class:BaseCache::CpuSidePort 299 virtual Tick recvAtomic(PacketPtr pkt) override; member in class:BaseCache::CpuSidePort 301 virtual void recvFunctional(PacketPtr pkt) override; member in class:BaseCache::CpuSidePort 303 virtual AddrRangeList getAddrRanges() const override; member in class:BaseCache::CpuSidePort 797 virtual void memWriteback() override; member in class:BaseCache 806 virtual void memInvalidate() override; member in class:BaseCache 1045 void regStats() override; member in class:BaseCache 1048 void regProbePoints() override; member in class:BaseCache 1054 void init() override; member in class:BaseCache 1057 PortID idx=InvalidPortID) override; member in class:BaseCache 1258 void serialize(CheckpointOut &cp) const override; member in class:BaseCache 1259 void unserialize(CheckpointIn &cp) override; member in class:BaseCache [all...] |
/gem5/src/arch/hsail/insts/ |
H A D | decl.hh | 757 void generateDisassembly() override 762 bool isVectorRegister(int operandIndex) override { return false; } 763 bool isCondRegister(int operandIndex) override { return false; } 764 bool isScalarRegister(int operandIndex) override { return false; } 765 bool isSrcOperand(int operandIndex) override { return false; } 766 bool isDstOperand(int operandIndex) override { return false; } 767 int getOperandSize(int operandIndex) override { return 0; } 770 getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override 775 int numSrcRegOperands() override { return 0; } 776 int numDstRegOperands() override { retur [all...] |
/gem5/src/dev/arm/ |
H A D | gic_v3_its.hh | 101 Port & getPort(const std::string &if_name, PortID idx) override; member in class:Gicv3Its 147 AddrRangeList getAddrRanges() const override; 149 Tick read(PacketPtr pkt) override; 150 Tick write(PacketPtr pkt) override; 152 DrainState drain() override; 153 void serialize(CheckpointOut & cp) const override; 154 void unserialize(CheckpointIn & cp) override; 408 void main(Yield &yield) override; member in class:Gicv3Its::ItsTranslation 488 void main(Yield &yield) override;
|
H A D | pl111.hh | 372 Tick read(PacketPtr pkt) override; member in class:Pl111 373 Tick write(PacketPtr pkt) override; member in class:Pl111 375 void serialize(CheckpointOut &cp) const override; member in class:Pl111 376 void unserialize(CheckpointIn &cp) override; member in class:Pl111 383 AddrRangeList getAddrRanges() const override; member in class:Pl111
|
/gem5/src/base/ |
H A D | addr_range.test.cc | 134 void SetUp() override 145 int getIndex(Addr addr) override 168 void SetUp() override 191 void SetUp() override 202 int getIndex(Addr addr) override
|
H A D | output.hh | 112 bool recreateable() const override { return _recreateable; } 126 void relocate(const OutputDirectory &dir) override; member in class:OutputFile
|
/gem5/src/dev/storage/ |
H A D | ide_disk.hh | 279 void regStats() override; member in class:IdeDisk 362 void serialize(CheckpointOut &cp) const override; member in class:IdeDisk 363 void unserialize(CheckpointIn &cp) override; member in class:IdeDisk
|
/gem5/src/dev/virtio/ |
H A D | fs9p.hh | 219 void serialize(CheckpointOut &cp) const override; member in class:VirtIO9PProxy 220 void unserialize(CheckpointIn &cp) override; member in class:VirtIO9PProxy 224 size_t size) override; member in class:VirtIO9PProxy
|
/gem5/ext/pybind11/tests/ |
H A D | test_exceptions.cpp | 16 virtual const char * what() const noexcept override {return message.c_str();} 25 virtual const char * what() const noexcept override {return message.c_str();} 44 virtual const char * what() const noexcept override {return message.c_str();}
|
/gem5/src/arch/alpha/ |
H A D | pagetable.hh | 145 void serialize(CheckpointOut &cp) const override; member in struct:AlphaISA::TlbEntry 146 void unserialize(CheckpointIn &cp) override; member in struct:AlphaISA::TlbEntry
|
/gem5/src/base/vnc/ |
H A D | vncserver.hh | 309 void setDirty() override; member in class:VncServer 310 void frameBufferResized() override; member in class:VncServer
|