Searched refs:override (Results 176 - 200 of 403) sorted by relevance

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/gem5/src/sim/
H A Dfd_entry.hh88 clone() const override
127 clone() const override
138 void serialize(CheckpointOut &cp) const override; member in class:FileFDEntry
139 void unserialize(CheckpointIn &cp) override; member in class:FileFDEntry
171 clone() const override
182 void serialize(CheckpointOut &cp) const override; member in class:PipeFDEntry
183 void unserialize(CheckpointIn &cp) override; member in class:PipeFDEntry
208 clone() const override
216 void serialize(CheckpointOut &cp) const override; member in class:DeviceFDEntry
217 void unserialize(CheckpointIn &cp) override; member in class:DeviceFDEntry
[all...]
/gem5/src/mem/
H A Dport.hh95 void bind(Port &peer) override; member in class:MasterPort
100 void unbind() override; member in class:MasterPort
106 * requests (e.g. a cache connected to a bus) has to override this
206 * coherent crossbar can override the behaviour.
224 recvAtomicSnoop(PacketPtr pkt) override
231 recvFunctionalSnoop(PacketPtr pkt) override
237 recvTimingSnoopReq(PacketPtr pkt) override
243 recvRetrySnoopResp() override
295 * responsible for. All slave ports must override this function
305 void unbind() override {}
411 Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) override; member in class:SlavePort
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H A Ddramsim2.hh192 DrainState drain() override; member in class:DRAMSim2
195 PortID idx=InvalidPortID) override; member in class:DRAMSim2
197 void init() override; member in class:DRAMSim2
198 void startup() override; member in class:DRAMSim2
H A Dcoherent_xbar.hh112 recvTimingReq(PacketPtr pkt) override
118 recvTimingSnoopResp(PacketPtr pkt) override
124 recvAtomic(PacketPtr pkt) override
130 recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) override
136 recvFunctional(PacketPtr pkt) override
142 getAddrRanges() const override
175 bool isSnooping() const override { return true; }
178 recvTimingResp(PacketPtr pkt) override
184 recvTimingSnoopReq(PacketPtr pkt) override
190 recvAtomicSnoop(PacketPtr pkt) override
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/gem5/src/arch/arm/
H A Dsemihosting.hh80 void serialize(CheckpointOut &cp) const override; member in class:ArmSemihosting
81 void unserialize(CheckpointIn &cp) override; member in class:ArmSemihosting
131 void serialize(CheckpointOut &cp) const override; member in class:ArmSemihosting::FileBase
132 void unserialize(CheckpointIn &cp) override; member in class:ArmSemihosting::FileBase
212 void serialize(CheckpointOut &cp) const override; member in class:ArmSemihosting::FileFeatures
213 void unserialize(CheckpointIn &cp) override; member in class:ArmSemihosting::FileFeatures
215 int64_t read(uint8_t *buffer, uint64_t size) override; member in class:ArmSemihosting::FileFeatures
216 int64_t seek(uint64_t pos) override; member in class:ArmSemihosting::FileFeatures
228 void serialize(CheckpointOut &cp) const override; member in class:ArmSemihosting::File
229 void unserialize(CheckpointIn &cp) override; member in class:ArmSemihosting::File
232 int64_t close() override; member in class:ArmSemihosting::File
233 bool isTTY() const override; member in class:ArmSemihosting::File
234 int64_t read(uint8_t *buffer, uint64_t size) override; member in class:ArmSemihosting::File
235 int64_t write(const uint8_t *buffer, uint64_t size) override; member in class:ArmSemihosting::File
236 int64_t seek(uint64_t pos) override; member in class:ArmSemihosting::File
237 int64_t flen() override; member in class:ArmSemihosting::File
[all...]
/gem5/ext/nomali/lib/
H A Dmali_t6xx.hh35 void setupControlIdRegisters(RegVector &regs) override; member in class:NoMali::MaliT6xxBase
/gem5/src/dev/arm/
H A Dpci_host.hh58 PciIntPin pin) const override; member in class:GenericArmPciHost
H A Dhdlcd.hh99 void regStats() override; member in class:HDLcd
101 void serialize(CheckpointOut &cp) const override; member in class:HDLcd
102 void unserialize(CheckpointIn &cp) override; member in class:HDLcd
104 void drainResume() override; member in class:HDLcd
107 Tick read(PacketPtr pkt) override; member in class:HDLcd
108 Tick write(PacketPtr pkt) override; member in class:HDLcd
110 AddrRangeList getAddrRanges() const override { return addrRanges; }
333 bool nextPixel(Pixel &p) override { return parent.pxlNext(p); }
335 void onVSyncBegin() override { return parent.pxlVSyncBegin(); }
336 void onVSyncEnd() override { retur
378 void serialize(CheckpointOut &cp) const override; member in class:HDLcd::DmaEngine
379 void unserialize(CheckpointIn &cp) override; member in class:HDLcd::DmaEngine
382 void onEndOfBlock() override; member in class:HDLcd::DmaEngine
383 void onIdle() override; member in class:HDLcd::DmaEngine
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H A Dkmi.hh133 Tick read(PacketPtr pkt) override; member in class:Pl050
134 Tick write(PacketPtr pkt) override; member in class:Pl050
136 void serialize(CheckpointOut &cp) const override; member in class:Pl050
137 void unserialize(CheckpointIn &cp) override; member in class:Pl050
H A Dgeneric_timer.hh103 void serialize(CheckpointOut &cp) const override; member in class:SystemCounter
104 void unserialize(CheckpointIn &cp) override; member in class:SystemCounter
181 void serialize(CheckpointOut &cp) const override; member in class:ArchTimer
182 void unserialize(CheckpointIn &cp) override; member in class:ArchTimer
185 DrainState drain() override; member in class:ArchTimer
186 void drainResume() override; member in class:ArchTimer
210 bool scheduleEvents() override {
222 void serialize(CheckpointOut &cp) const override; member in class:GenericTimer
223 void unserialize(CheckpointIn &cp) override; member in class:GenericTimer
289 void setMiscReg(int misc_reg, RegVal val) override; member in class:GenericTimerISA
290 RegVal readMiscReg(int misc_reg) override; member in class:GenericTimerISA
302 void serialize(CheckpointOut &cp) const override; member in class:GenericTimerMem
303 void unserialize(CheckpointIn &cp) override; member in class:GenericTimerMem
307 Tick read(PacketPtr pkt) override; member in class:GenericTimerMem
308 Tick write(PacketPtr pkt) override; member in class:GenericTimerMem
[all...]
H A Dflash_device.hh65 DrainState drain() override; member in class:FlashDevice
68 void serialize(CheckpointOut &cp) const override; member in class:FlashDevice
69 void unserialize(CheckpointIn &cp) override; member in class:FlashDevice
110 void initializeMemory(uint64_t disk_size, uint32_t sector_size) override
116 Callback *event) override
122 Callback *event) override
150 void regStats() override; member in class:FlashDevice
/gem5/src/arch/sparc/
H A Dsystem.hh51 void initState() override; member in class:SparcSystem
57 void serializeSymtab(CheckpointOut &cp) const override; member in class:SparcSystem
58 void unserializeSymtab(CheckpointIn &cp) override; member in class:SparcSystem
127 fixFuncEventAddr(Addr addr) override
/gem5/src/arch/arm/kvm/
H A Darmv8_cpu.hh87 void startup() override; member in class:ArmV8KvmCPU
89 void dump() const override; member in class:ArmV8KvmCPU
92 void updateKvmState() override; member in class:ArmV8KvmCPU
93 void updateThreadContext() override; member in class:ArmV8KvmCPU
/gem5/src/arch/sparc/insts/
H A Dinteger.hh55 Addr pc, const SymbolTable *symtab) const override; member in class:SparcISA::IntOp
76 Addr pc, const SymbolTable *symtab) const override; member in class:SparcISA::IntOpImm
79 const SymbolTable *symtab) const override; member in class:SparcISA::IntOpImm
128 Addr pc, const SymbolTable *symtab) const override; member in class:SparcISA::SetHi
H A Dpriv.hh50 Addr pc, const SymbolTable *symtab) const override; member in class:SparcISA::Priv
71 Addr pc, const SymbolTable *symtab) const override; member in class:SparcISA::RdPriv
81 Addr pc, const SymbolTable *symtab) const override; member in class:SparcISA::WrPriv
110 Addr pc, const SymbolTable *symtab) const override; member in class:SparcISA::WrPrivImm
/gem5/src/arch/power/insts/
H A Dmisc.hh53 Addr pc, const SymbolTable *symtab) const override; member in class:PowerISA::MiscOp
H A Dbranch.hh89 PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override; member in class:PowerISA::BranchPCRel
95 Addr pc, const SymbolTable *symtab) const override; member in class:PowerISA::BranchPCRel
119 PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override; member in class:PowerISA::BranchNonPCRel
125 Addr pc, const SymbolTable *symtab) const override; member in class:PowerISA::BranchNonPCRel
198 PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override; member in class:PowerISA::BranchPCRelCond
204 Addr pc, const SymbolTable *symtab) const override; member in class:PowerISA::BranchPCRelCond
228 PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override; member in class:PowerISA::BranchNonPCRelCond
234 Addr pc, const SymbolTable *symtab) const override; member in class:PowerISA::BranchNonPCRelCond
250 PowerISA::PCState branchTarget(ThreadContext *tc) const override; member in class:PowerISA::BranchRegCond
256 Addr pc, const SymbolTable *symtab) const override; member in class:PowerISA::BranchRegCond
[all...]
/gem5/src/cpu/testers/traffic_gen/
H A Dpygen.hh60 std::shared_ptr<BaseGen> nextGenerator() override; member in class:PyTrafficGen
/gem5/src/gpu-compute/
H A Dscheduling_policy.hh69 chooseWave(std::vector<Wavefront*> *sched_list) override
/gem5/util/systemc/systemc_within_gem5/systemc_simple_object/
H A Dfeeder.hh68 void startup() override; member in class:Feeder
/gem5/src/mem/cache/prefetch/
H A Dslim_ampm.hh62 std::vector<AddrPriority> &addresses) override; member in class:SlimAMPMPrefetcher
/gem5/src/mem/qos/
H A Dmem_sink.hh131 DrainState drain() override; member in class:QoS::MemSinkCtrl
140 Port &getPort(const std::string &if_name, PortID=InvalidPortID) override; member in class:QoS::MemSinkCtrl
145 void init() override; member in class:QoS::MemSinkCtrl
242 void regStats() override; member in class:QoS::MemSinkCtrl
H A Dq_policy.hh128 selectPacket(PacketQueue* queue) override
149 selectPacket(PacketQueue* queue) override
168 void enqueuePacket(PacketPtr pkt) override; member in class:QoS::LrgQueuePolicy
177 selectPacket(PacketQueue* queue) override; member in class:QoS::LrgQueuePolicy
/gem5/src/arch/generic/
H A Dtlb.hh152 void demapPage(Addr vaddr, uint64_t asn) override; member in class:GenericTLB
155 const RequestPtr &req, ThreadContext *tc, Mode mode) override; member in class:GenericTLB
158 Translation *translation, Mode mode) override; member in class:GenericTLB
161 const RequestPtr &req, ThreadContext *tc, Mode mode) const override; member in class:GenericTLB
/gem5/src/dev/net/
H A Ddist_etherlink.hh98 void serialize(CheckpointOut &cp) const override; member in class:DistEtherLink::Link
99 void unserialize(CheckpointIn &cp) override; member in class:DistEtherLink::Link
227 PortID idx=InvalidPortID) override; member in class:DistEtherLink
229 virtual void init() override; member in class:DistEtherLink
230 virtual void startup() override; member in class:DistEtherLink
232 void serialize(CheckpointOut &cp) const override; member in class:DistEtherLink
233 void unserialize(CheckpointIn &cp) override; member in class:DistEtherLink

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