/gem5/src/kern/ |
H A D | kernel_stats.hh | 63 void serialize(CheckpointOut &cp) const override {} 64 void unserialize(CheckpointIn &cp) override {}
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/gem5/src/dev/net/ |
H A D | tcp_iface.hh | 126 const EthPacketPtr &packet) override; member in class:TCPIface 128 void sendCmd(const Header &header) override; member in class:TCPIface 130 bool recvHeader(Header &header) override; member in class:TCPIface 132 void recvPacket(const Header &header, EthPacketPtr &packet) override; member in class:TCPIface 134 void initTransport() override; member in class:TCPIface 153 ~TCPIface() override; member in class:TCPIface
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/gem5/src/dev/arm/ |
H A D | timer_a9global.hh | 137 void serialize(CheckpointOut &cp) const override; member in class:A9GlobalTimer::Timer 138 void unserialize(CheckpointIn &cp) override; member in class:A9GlobalTimer::Timer 165 Tick read(PacketPtr pkt) override; member in class:A9GlobalTimer 172 Tick write(PacketPtr pkt) override; member in class:A9GlobalTimer 174 void serialize(CheckpointOut &cp) const override; member in class:A9GlobalTimer 175 void unserialize(CheckpointIn &cp) override; member in class:A9GlobalTimer
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H A D | timer_sp804.hh | 124 void serialize(CheckpointOut &cp) const override; member in class:Sp804::Timer 125 void unserialize(CheckpointIn &cp) override; member in class:Sp804::Timer 153 Tick read(PacketPtr pkt) override; member in class:Sp804 160 Tick write(PacketPtr pkt) override; member in class:Sp804 163 void serialize(CheckpointOut &cp) const override; member in class:Sp804 164 void unserialize(CheckpointIn &cp) override; member in class:Sp804
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H A D | timer_cpulocal.hh | 149 void serialize(CheckpointOut &cp) const override; member in class:CpuLocalTimer::Timer 150 void unserialize(CheckpointIn &cp) override; member in class:CpuLocalTimer::Timer 175 void init() override; member in class:CpuLocalTimer 182 Tick read(PacketPtr pkt) override; member in class:CpuLocalTimer 189 Tick write(PacketPtr pkt) override; member in class:CpuLocalTimer 191 void serialize(CheckpointOut &cp) const override; member in class:CpuLocalTimer 192 void unserialize(CheckpointIn &cp) override; member in class:CpuLocalTimer
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H A D | base_gic.hh | 71 void init() override; member in class:BaseGic 151 ArmInterruptPin* get(ThreadContext *tc = nullptr) override; member in class:ArmSPIGen 166 ArmInterruptPin* get(ThreadContext* tc = nullptr) override; member in class:ArmPPIGen 228 void raise() override; member in class:ArmSPI 229 void clear() override; member in class:ArmSPI 239 void raise() override; member in class:ArmPPI 240 void clear() override; member in class:ArmPPI
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/gem5/src/dev/serial/ |
H A D | uart8250.hh | 91 Tick read(PacketPtr pkt) override; member in class:Uart8250 92 Tick write(PacketPtr pkt) override; member in class:Uart8250 93 AddrRangeList getAddrRanges() const override; member in class:Uart8250 98 void dataAvailable() override; member in class:Uart8250 107 void serialize(CheckpointOut &cp) const override; member in class:Uart8250 108 void unserialize(CheckpointIn &cp) override; member in class:Uart8250
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/gem5/src/arch/sparc/insts/ |
H A D | micro.hh | 61 Addr pc, const SymbolTable *symtab) const override; member in class:SparcISA::SparcMacroInst 66 fetchMicroop(MicroPC upc) const override 73 execute(ExecContext *, Trace::InstRecord *) const override 79 initiateAcc(ExecContext *, Trace::InstRecord *) const override 85 completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const override 103 advancePC(SparcISA::PCState &pcState) const override
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/gem5/src/arch/arm/insts/ |
H A D | pseudo.hh | 60 Trace::InstRecord *traceData) const override; member in class:DecoderFaultInst 63 Addr pc, const SymbolTable *symtab) const override; member in class:DecoderFaultInst 86 Trace::InstRecord *traceData) const override; member in class:FailUnimplemented 89 Addr pc, const SymbolTable *symtab) const override; member in class:FailUnimplemented 116 Trace::InstRecord *traceData) const override; member in class:WarnUnimplemented 119 Addr pc, const SymbolTable *symtab) const override; member in class:WarnUnimplemented
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H A D | branch64.hh | 59 const ArmISA::PCState &branchPC) const override; member in class:ArmISA::BranchImm64 65 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::BranchImm64 81 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::BranchImmCond64 97 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::BranchReg64 110 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::BranchRet64 122 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::BranchEret64 139 const ArmISA::PCState &branchPC) const override; member in class:ArmISA::BranchImmReg64 145 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::BranchImmReg64 165 const ArmISA::PCState &branchPC) const override; member in class:ArmISA::BranchImmImmReg64 171 Addr pc, const SymbolTable *symtab) const override; member in class:ArmISA::BranchImmImmReg64 [all...] |
/gem5/src/sim/ |
H A D | sim_events.hh | 90 void process() override; // process event member in class:LocalSimLoopExitEvent 92 const char *description() const override; member in class:LocalSimLoopExitEvent 94 void serialize(CheckpointOut &cp) const override; member in class:LocalSimLoopExitEvent 95 void unserialize(CheckpointIn &cp) override; member in class:LocalSimLoopExitEvent 112 void process() override; // process event member in class:CountedExitEvent 114 const char *description() const override; member in class:CountedExitEvent
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/gem5/src/mem/cache/ |
H A D | write_queue_entry.hh | 95 bool sendPacket(BaseCache &cache) override; member in class:WriteQueueEntry 153 Target *getTarget() override 174 const std::string &prefix = "") const override; member in class:WriteQueueEntry 183 bool matchBlockAddr(const Addr addr, const bool is_secure) const override; member in class:WriteQueueEntry 184 bool matchBlockAddr(const PacketPtr pkt) const override; member in class:WriteQueueEntry 185 bool conflictAddr(const QueueEntry* entry) const override; member in class:WriteQueueEntry
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/gem5/src/dev/x86/ |
H A D | i8259.hh | 48 void init() override; member in class:X86ISA::I8259 96 getPort(const std::string &if_name, PortID idx=InvalidPortID) override 106 Tick read(PacketPtr pkt) override; member in class:X86ISA::I8259 107 Tick write(PacketPtr pkt) override; member in class:X86ISA::I8259 126 void serialize(CheckpointOut &cp) const override; member in class:X86ISA::I8259 127 void unserialize(CheckpointIn &cp) override; member in class:X86ISA::I8259
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H A D | i8254.hh | 74 getPort(const std::string &if_name, PortID idx=InvalidPortID) override 96 Tick read(PacketPtr pkt) override; member in class:X86ISA::I8254 98 Tick write(PacketPtr pkt) override; member in class:X86ISA::I8254 124 void serialize(CheckpointOut &cp) const override; member in class:X86ISA::I8254 125 void unserialize(CheckpointIn &cp) override; member in class:X86ISA::I8254 127 void startup() override; member in class:X86ISA::I8254
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H A D | cmos.hh | 86 getPort(const std::string &if_name, PortID idx=InvalidPortID) override 94 Tick read(PacketPtr pkt) override; member in class:X86ISA::Cmos 96 Tick write(PacketPtr pkt) override; member in class:X86ISA::Cmos 98 void startup() override; member in class:X86ISA::Cmos 100 void serialize(CheckpointOut &cp) const override; member in class:X86ISA::Cmos 101 void unserialize(CheckpointIn &cp) override; member in class:X86ISA::Cmos
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/gem5/src/dev/storage/ |
H A D | disk_image.hh | 85 void notifyFork() override; member in class:RawDiskImage 90 std::streampos size() const override; member in class:RawDiskImage 92 std::streampos read(uint8_t *data, std::streampos offset) const override; member in class:RawDiskImage 93 std::streampos write(const uint8_t *data, std::streampos offset) override; member in class:RawDiskImage 128 void notifyFork() override; member in class:CowDiskImage 136 void serialize(CheckpointOut &cp) const override; member in class:CowDiskImage 137 void unserialize(CheckpointIn &cp) override; member in class:CowDiskImage 139 std::streampos size() const override; member in class:CowDiskImage 141 std::streampos read(uint8_t *data, std::streampos offset) const override; member in class:CowDiskImage 142 std::streampos write(const uint8_t *data, std::streampos offset) override; member in class:CowDiskImage [all...] |
/gem5/src/dev/ |
H A D | pixelpump.hh | 66 void serialize(CheckpointOut &cp) const override; member in struct:DisplayTimings 67 void unserialize(CheckpointIn &cp) override; member in struct:DisplayTimings 155 void serialize(CheckpointOut &cp) const override; member in class:BasePixelPump 156 void unserialize(CheckpointIn &cp) override; member in class:BasePixelPump 267 DrainState drain() override; member in class:BasePixelPump::PixelEvent 268 void drainResume() override; member in class:BasePixelPump::PixelEvent 270 void serialize(CheckpointOut &cp) const override; member in class:BasePixelPump::PixelEvent 271 void unserialize(CheckpointIn &cp) override; member in class:BasePixelPump::PixelEvent 273 const std::string name() const override { return _name; } 274 void process() override { [all...] |
/gem5/src/systemc/tlm_bridge/ |
H A D | gem5_to_tlm.hh | 99 getAddrRanges() const override 104 recvAtomic(PacketPtr pkt) override 109 recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) override 114 recvFunctional(PacketPtr pkt) override 119 recvTimingReq(PacketPtr pkt) override 124 tryTiming(PacketPtr pkt) override 129 recvTimingSnoopResp(PacketPtr pkt) override 133 void recvRespRetry() override { bridge.recvRespRetry(); } 195 ::Port &gem5_getPort(const std::string &if_name, int idx=-1) override; member in class:sc_gem5::Gem5ToTlmBridge 206 void before_end_of_elaboration() override; member in class:sc_gem5::Gem5ToTlmBridge [all...] |
/gem5/src/cpu/simple/ |
H A D | base.hh | 96 void wakeup(ThreadID tid) override; member in class:BaseSimpleCPU 97 void init() override; member in class:BaseSimpleCPU 137 void haltContext(ThreadID thread_num) override; member in class:BaseSimpleCPU 140 void regStats() override; member in class:BaseSimpleCPU 141 void resetStats() override; member in class:BaseSimpleCPU 143 void startup() override; member in class:BaseSimpleCPU 174 Counter totalInsts() const override; member in class:BaseSimpleCPU 175 Counter totalOps() const override; member in class:BaseSimpleCPU 177 void serializeThread(CheckpointOut &cp, ThreadID tid) const override; member in class:BaseSimpleCPU 178 void unserializeThread(CheckpointIn &cp, ThreadID tid) override; member in class:BaseSimpleCPU [all...] |
/gem5/src/cpu/kvm/ |
H A D | base.hh | 67 * this class. The most basic CPU models only need to override the 84 void init() override; member in class:BaseKvmCPU 85 void startup() override; member in class:BaseKvmCPU 86 void regStats() override; member in class:BaseKvmCPU 88 void serializeThread(CheckpointOut &cp, ThreadID tid) const override; member in class:BaseKvmCPU 89 void unserializeThread(CheckpointIn &cp, ThreadID tid) override; member in class:BaseKvmCPU 91 DrainState drain() override; member in class:BaseKvmCPU 92 void drainResume() override; member in class:BaseKvmCPU 93 void notifyFork() override; member in class:BaseKvmCPU 95 void switchOut() override; member in class:BaseKvmCPU 96 void takeOverFrom(BaseCPU *cpu) override; member in class:BaseKvmCPU 98 void verifyMemoryMode() const override; member in class:BaseKvmCPU 103 void wakeup(ThreadID tid = 0) override; member in class:BaseKvmCPU 104 void activateContext(ThreadID thread_num) override; member in class:BaseKvmCPU 105 void suspendContext(ThreadID thread_num) override; member in class:BaseKvmCPU 107 void haltContext(ThreadID thread_num) override; member in class:BaseKvmCPU 110 ThreadContext *getContext(int tn) override; member in class:BaseKvmCPU 112 Counter totalInsts() const override; member in class:BaseKvmCPU 113 Counter totalOps() const override; member in class:BaseKvmCPU 606 bool recvTimingResp(PacketPtr pkt) override; member in class:BaseKvmCPU::KVMCpuPort 608 void recvReqRetry() override; member in class:BaseKvmCPU::KVMCpuPort [all...] |
/gem5/src/mem/ruby/system/ |
H A D | RubySystem.hh | 77 void regStats() override { 82 void resetStats() override; member in class:RubySystem 84 void memWriteback() override; member in class:RubySystem 85 void serialize(CheckpointOut &cp) const override; member in class:RubySystem 86 void unserialize(CheckpointIn &cp) override; member in class:RubySystem 87 void drainResume() override; member in class:RubySystem 89 void startup() override; member in class:RubySystem
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/gem5/src/cpu/o3/ |
H A D | dyn_inst.hh | 140 readMiscReg(int misc_reg) override 149 setMiscReg(int misc_reg, RegVal val) override 174 readMiscRegOperand(const StaticInst *si, int idx) override 185 setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override 255 void syscall(int64_t callnum, Fault *fault) override; member in class:BaseO3DynInst 271 readIntRegOperand(const StaticInst *si, int idx) override 277 readFloatRegOperandBits(const StaticInst *si, int idx) override 283 readVecRegOperand(const StaticInst *si, int idx) const override 292 getWritableVecRegOperand(const StaticInst *si, int idx) override 301 readVec8BitLaneOperand(const StaticInst *si, int idx) const override [all...] |
/gem5/src/arch/riscv/ |
H A D | faults.hh | 106 FaultName name() const override { return _name; } 112 void invoke(ThreadContext *tc, const StaticInstPtr &inst) override; member in class:RiscvISA::RiscvFault 122 FaultName name() const override { return _name; } 125 StaticInst::nullStaticInstPtr) override; member in class:RiscvISA::Reset 145 RegVal trap_value() const override { return _inst; } 155 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; member in class:RiscvISA::UnknownInstFault 168 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; member in class:RiscvISA::IllegalInstFault 182 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; member in class:RiscvISA::UnimplementedFault 196 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; member in class:RiscvISA::IllegalFrmFault 209 RegVal trap_value() const override { retur 223 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; member in class:RiscvISA::BreakpointFault 248 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; member in class:RiscvISA::SyscallFault [all...] |
/gem5/src/mem/cache/tags/ |
H A D | fa_lru.hh | 102 std::string print() const override; member in class:FALRUBlk 165 void tagsInit() override; member in class:FALRU 170 void regStats() override; member in class:FALRU 176 void invalidate(CacheBlk *blk) override; member in class:FALRU 196 CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override; member in class:FALRU 205 CacheBlk* findBlock(Addr addr, bool is_secure) const override; member in class:FALRU 214 ReplaceableEntry* findBlockBySetAndWay(int set, int way) const override; member in class:FALRU 228 std::vector<CacheBlk*>& evict_blks) const override; member in class:FALRU 236 void insertBlock(const PacketPtr pkt, CacheBlk *blk) override; member in class:FALRU 244 Addr extractTag(Addr addr) const override [all...] |
/gem5/src/cpu/checker/ |
H A D | cpu.hh | 96 void init() override; member in class:CheckerCPU 109 getDataPort() override 118 getInstPort() override 163 virtual Counter totalInsts() const override 168 virtual Counter totalOps() const override 177 void serialize(CheckpointOut &cp) const override; member in class:CheckerCPU 178 void unserialize(CheckpointIn &cp) override; member in class:CheckerCPU 192 readIntRegOperand(const StaticInst *si, int idx) override 200 readFloatRegOperandBits(const StaticInst *si, int idx) override 211 readVecRegOperand(const StaticInst *si, int idx) const override 560 override; member in class:CheckerCPU 565 override; member in class:CheckerCPU [all...] |