Searched refs:interrupts (Results 26 - 33 of 33) sorted by relevance

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/gem5/src/cpu/
H A DBaseCPU.py190 interrupts = ArchInterruptsParam([], "Interrupt Controller") variable in class:BaseCPU
222 _uncached_slave_ports += ["interrupts[0].pio",
223 "interrupts[0].int_slave"]
224 _uncached_master_ports += ["interrupts[0].int_master"]
227 self.interrupts = [ArchInterrupts() for i in range(self.numThreads)]
/gem5/src/arch/sparc/
H A Dtlb.cc37 #include "arch/sparc/interrupts.hh"
1020 SparcISA::Interrupts * interrupts = local
1023 pkt->setBE(interrupts->get_vec(IT_INT_VEC));
1028 SparcISA::Interrupts * interrupts = local
1031 temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
1276 // clear all the interrupts that aren't set in the write
1277 SparcISA::Interrupts * interrupts = local
1280 while (interrupts->get_vec(IT_INT_VEC) & data) {
1281 msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
/gem5/src/cpu/kvm/
H A Dx86_cpu.cc793 // DPL of SS correctly when taking interrupts, so we need to fix
1140 // call across threads, we might still lose interrupts unless
1143 EventQueue::ScopedMigration migrate(interrupts[0]->eventQueue());
1144 fault = interrupts[0]->getInterrupt(tc);
1145 interrupts[0]->updateIntrInfo(tc);
1188 if (interrupts[0]->checkInterruptsRaw()) {
1189 if (interrupts[0]->hasPendingUnmaskable()) {
1197 // interrupts (e.g., by doing a CPU handover). Let's sync
1199 // interrupts that should be delivered now.
1201 if (interrupts[
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/gem5/util/stats/
H A Dstats.py387 interrupts = system.run0.kern.faults[4]
388 output.stat = interrupts / kbytes
/gem5/src/cpu/simple/
H A Dbase.cc456 Fault interrupt = interrupts[curThread]->getInterrupt(tc);
460 interrupts[curThread]->updateIntrInfo(tc);
/gem5/src/cpu/o3/
H A Dcpu.cc367 if (!params->switched_out && interrupts.empty()) {
889 // Check if there are any outstanding interrupts
890 return this->interrupts[0]->getInterrupt(this->threadContexts[0]);
897 // Check for interrupts here. For now can copy the code that
899 // is the one that handles the interrupts.
901 // @todo: Allow other threads to handle interrupts.
904 this->interrupts[0]->updateIntrInfo(this->threadContexts[0]);
/gem5/src/dev/arm/
H A DRealView.py123 int_count = Param.Unsigned("Maximum number of interrupts used by this host")
175 interrupts = []
187 interrupts += self.pciFdtAddr(device=i, addr=0) + \
191 node.append(FdtPropertyWords("interrupt-map", interrupts))
412 node.append(FdtPropertyWords("interrupts", [
914 model in the future. Such devices should normally have interrupts in
968 0- 15: Software generated interrupts (SGIs)
/gem5/src/arch/arm/kvm/
H A Darm_cpu.cc273 bool simFIQ(interrupts[0]->checkRaw(INT_FIQ));
274 bool simIRQ(interrupts[0]->checkRaw(INT_IRQ));

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