Searched refs:event (Results 26 - 50 of 130) sorted by relevance

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/gem5/src/systemc/tests/systemc/misc/v1.0/dash4/
H A Ddist.cpp100 // Implement reset.event():
121 if (total_dist.event())
124 if (partial_dist.event())
/gem5/src/systemc/tests/systemc/misc/v1.0/dash5/
H A Ddist.cpp100 // Implement reset.event():
121 if (total_dist.event())
124 if (partial_dist.event())
/gem5/src/systemc/tests/systemc/misc/v1.0/dash6/
H A Ddist.cpp100 // Implement reset.event():
121 if (total_dist.event())
124 if (partial_dist.event())
/gem5/src/systemc/tests/systemc/misc/v1.0/dash7/
H A Ddist.cpp100 // Implement reset.event():
121 if (total_dist.event())
124 if (partial_dist.event())
/gem5/src/systemc/tests/systemc/misc/v1.0/dash8/
H A Ddist.cpp100 // Implement reset.event():
121 if (total_dist.event())
124 if (partial_dist.event())
/gem5/src/systemc/tests/systemc/misc/v1.0/dash9/
H A Ddist.cpp100 // Implement reset.event():
121 if (total_dist.event())
124 if (partial_dist.event())
/gem5/src/sim/
H A Ddvfs_handler.cc84 // Create a dedicated event slot per known domain ID
85 UpdateEvent *event = &updatePerfLevelEvents[domain_id]; local
86 event->domainIDToSet = d->domainID();
138 DPRINTF(DVFS, "DVFS: Overwriting the previous DVFS event.\n");
154 DPRINTF(DVFS, "DVFS: Update for perf event scheduled for %ld\n", when);
208 // ensuring that the data associated with any pending update event is saved
214 const UpdateEvent *event = &ev_pair.second; local
216 assert(id == event->domainIDToSet);
218 perf_levels.push_back(event->perfLevelToSet);
219 whens.push_back(event
247 UpdateEvent *event = &updatePerfLevelEvents[domain_ids[i]]; local
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H A Deventq.hh61 //! event to scheduled on Queue A which is generated by an event on
65 //! Current number of allocated main event queues.
68 //! Array for main event queues.
71 //! The current event queue for the running thread. Access to this queue
111 static const FlagsType IsExitEvent = 0x0010; // special exit event
112 static const FlagsType IsMainQueue = 0x0020; // on main event queue
137 /// CPU switches schedule the new CPU's tick event for the
138 /// same cycle (after unscheduling the old CPU's tick event).
151 /// DVFS update event lead
744 schedule(Event &event, Tick when) argument
750 deschedule(Event &event) argument
756 reschedule(Event &event, Tick when, bool always = false) argument
762 schedule(Event *event, Tick when) argument
768 deschedule(Event *event) argument
774 reschedule(Event *event, Tick when, bool always = false) argument
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/gem5/src/mem/slicc/ast/
H A DTransitionDeclAST.py67 for event in self.events:
68 if event not in machine.events:
69 self.error("Invalid event: %s is not part of machine: %s" % \
70 (event, machine))
71 t = Transition(self.symtab, machine, state, event, next_state,
/gem5/src/learning_gem5/part2/
H A Dgoodbye_object.hh47 /// An event that wraps the above function
48 EventFunctionWrapper event; member in class:GoodbyeObject
52 * function will enqueue another event to continue filling.
/gem5/src/python/m5/
H A Devent.py46 import _m5.event
48 from _m5.event import GlobalSimLoopExitEvent as SimExit
49 from _m5.event import PyEvent as Event
50 from _m5.event import getEventQueue, setEventQueue
H A D__init__.py59 from .event import *
/gem5/util/systemc/systemc_within_gem5/systemc_simple_object/
H A Dfeeder.hh66 EventWrapper<Feeder, &Feeder::feed> event; member in class:Feeder
/gem5/src/systemc/core/
H A Dscheduler.hh71 * schedules an event to be run at time 0 with a slightly elevated priority
72 * so that it happens before any "normal" event.
74 * When that t0 event happens, it calls the schedulers prepareForInit method
77 * happens after any "normal" event.
95 * of the same event, there's no chance for other events to intervene and
111 * If no processes became runnable, the event queue will continue to process
112 * events until it comes across an event which represents all the timed
121 * cycle's delta notification phase, an event is scheduled with a lower than
125 * event will happen before the next readyEvent which would start the next
131 * For that, a stop event wit
240 schedule(ScEvent *event, const ::sc_core::sc_time &delay) argument
265 deschedule(ScEvent *event) argument
394 schedule(::Event *event, Tick tick) argument
402 schedule(::Event *event) argument
405 deschedule(::Event *event) argument
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H A Dsensitivity.cc32 #include "systemc/core/event.hh"
127 s->addToEvent(s->event);
135 s->addToEvent(s->event);
152 s->addToEvent(s->event);
193 s->addToEvent(s->event);
202 for (auto event: s->events)
203 s->addToEvent(event);
211 for (auto event: s->events)
212 s->addToEvent(event);
/gem5/src/systemc/tests/systemc/misc/sim_tests/multtrans/multtrans0/
H A Dmulttrans0.cpp66 wait(); // until the first real event
108 if (data_i1.event()) {
109 if (data_i2.event()) {
119 else if (data_i2.event()) {
127 if (data_i2.event()) {
128 if (data_i1.event()) {
145 if (data_i1.event()) {
146 if (data_i2.event()) {
/gem5/src/dev/net/
H A Dethertap.cc86 // Ensure that our event queue is active. It may not be since we get
95 : SimObject(p), buflen(p->bufsz), dump(p->dump), event(NULL),
106 delete event;
118 if (event) {
121 event->serialize(cp);
137 event = new TapEvent(this, 0, 0);
138 event->unserialize(cp);
139 if (event->queued())
140 pollQueue.schedule(event);
148 assert(!event);
242 Event *event; member in class:TapListener
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/gem5/ext/sst/
H A DExtSlave.cc145 MemEvent* event = dynamic_cast<MemEvent*>(ev); local
146 if (!event) {
151 Event::id_type id = event->getID();
159 pkt->setData(event->getPayload().data());
163 pkt->req->setExtraData(event->isAtomic());
173 Command cmd = event->getCmd();
179 event->getAddr(), event->getSize(), 0, 0);
188 delete event;
/gem5/src/base/
H A Dpollevent.cc141 PollQueue::remove(PollEvent *event) argument
147 if (*i == event) {
150 event->queue = NULL;
161 PollQueue::schedule(PollEvent *event) argument
163 if (event->queue)
166 event->queue = this;
167 events.push_back(event);
168 setupAsyncIO(event->pfd.fd, true);
171 // if this is the first time that we've scheduled an event, create
251 /* Wake up some event queu
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/gem5/src/systemc/tests/systemc/kernel/dynamic_processes/test03/
H A Dtest03.cpp27 // test error message for wait() on dynamic method process handle's event.
63 module1(sc_module_name name, sc_event& event) : sc_module(name), argument
64 ev(event)
/gem5/src/systemc/tests/systemc/compliance_1666/test234/
H A Dtest234.cpp7 // 34) event finder on multiport
11 virtual const sc_event& event() const = 0;
16 virtual const sc_event& event() const { return ev; } function in struct:Chan
24 return *new sc_event_finder_t<i_f>( *this, &i_f::event );
55 sensitive << mp[i]->event();
/gem5/src/dev/arm/
H A Dflash_device.hh116 Callback *event) override
118 accessDevice(address, amount, event, ActionRead);
122 Callback *event) override
124 accessDevice(address, amount, event, ActionWrite);
131 void accessDevice(uint64_t address, uint32_t amount, Callback *event,
194 /** Completion event */
/gem5/src/dev/
H A Dmc146818.cc96 : EventManager(em), _name(n), event(this, frequency), tickEvent(this)
116 deschedule(event);
129 assert(!event.scheduled());
133 schedule(event, curTick() + event.offset);
212 if (!event.scheduled())
213 event.scheduleIntr();
215 if (event.scheduled())
216 deschedule(event);
282 Tick rtcTimerInterruptTickOffset = event
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H A Dintel_8254_timer.cc102 : _name(name), num(_num), event(this), running(false),
107 offset = period * event.getInterval();
124 int clocks = event.clocksLeft();
176 if (event.scheduled())
177 parent->deschedule(event);
191 offset = period * event.getInterval();
194 event.setTo(period);
244 if (event.scheduled())
245 event_tick_offset = event.when() - curTick();
262 assert(!event
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H A Ddma_device.hh84 * packet is part of is complete, then signal the completion event
88 * @param delay Additional delay for scheduling the completion event
156 dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
160 dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
179 void dmaWrite(Addr addr, int size, Event *event, uint8_t *data, argument
182 dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data,
186 void dmaWrite(Addr addr, int size, Event *event, uint8_t *data, argument
189 dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
192 void dmaRead(Addr addr, int size, Event *event, uint8_t *data, argument
195 dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, dat
199 dmaRead(Addr addr, int size, Event *event, uint8_t *data, Tick delay = 0) argument
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