/gem5/src/dev/arm/ |
H A D | smmu_v3_proc.cc | 168 next_proc->scheduleWakeup(curTick()); 187 it->scheduleWakeup(curTick());
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H A D | timer_sp804.cc | 95 time = zeroEvent.when() - curTick(); 192 parent->schedule(zeroEvent, curTick() + time); 193 DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick() + time);
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/gem5/src/mem/ |
H A D | packet_queue.cc | 114 assert(when >= curTick()); 167 when = std::max(when, curTick() + 1);
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/gem5/src/sim/ |
H A D | pseudo_inst.cc | 259 tc->quiesceTick(curTick() + SimClock::Int::ns * ns); 282 return curTick() / SimClock::Int::ns; 307 Tick when = curTick() + delay * SimClock::Int::ns; 316 Tick when = curTick() + delay * SimClock::Int::ns; 442 Tick when = curTick() + delay * SimClock::Int::ns; 456 Tick when = curTick() + delay * SimClock::Int::ns; 470 Tick when = curTick() + delay * SimClock::Int::ns; 484 Tick when = curTick() + delay * SimClock::Int::ns;
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H A D | global_event.cc | 158 schedule(curTick() + repeat);
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/gem5/src/mem/probes/ |
H A D | mem_trace.cc | 114 pkt_msg.set_tick(curTick());
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/gem5/src/cpu/testers/rubytest/ |
H A D | Check.cc | 111 m_tester_ptr->masterId(), curTick(), m_pc); 149 m_tester_ptr->masterId(), curTick(), m_pc); 182 writeAddr, 1, flags, m_tester_ptr->masterId(), curTick(), m_pc); 246 m_tester_ptr->masterId(), curTick(), m_pc);
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/gem5/src/gpu-compute/ |
H A D | shader.cc | 153 tick_cnt = curTick(); 154 box_tick_cnt = curTick() - start_tick_cnt; 193 schedule(tickEvent, curTick() + this->ticks(1)); 329 schedule(tickEvent, curTick() + ticks(1));
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H A D | gpu_tlb.cc | 1053 accessCycles -= (curTick() * req_cnt); 1054 localCycles -= curTick(); 1107 DPRINTF(GPUTLB, "schedule translationReturnEvent @ curTick %d\n", 1108 curTick() + this->ticks(hitLatency)); 1110 schedule(tlb_event, curTick() + this->ticks(hitLatency)); 1236 schedule(cleanupEvent, curTick()); 1263 accessCycles += (req_cnt * curTick()); 1264 localCycles += curTick(); 1271 accessCycles += (req_cnt*curTick()); 1272 localCycles += curTick(); [all...] |
/gem5/src/arch/riscv/ |
H A D | locked_mem.hh | 126 curTick(), xc->contextId(), stCondFailures);
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/gem5/configs/learning_gem5/part1/ |
H A D | simple.py | 114 print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))
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/gem5/configs/learning_gem5/part2/ |
H A D | simple_cache.py | 108 print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))
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H A D | simple_memobj.py | 106 print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))
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/gem5/src/mem/ruby/system/ |
H A D | RubySystem.cc | 148 Tick curtick_original = curTick(); 167 enqueueRubyEvent(curTick()); 176 // Restore curTick 180 // done after setting curTick back to its original value so that events do 354 Tick curtick_original = curTick(); 357 // set curTick to 0 and reset Ruby System's clock 362 enqueueRubyEvent(curTick()); 374 // Restore curTick and Ruby System's clock
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H A D | RubyPort.cc | 164 pkt, curTick() + rp->m_ruby_system->clockPeriod()); 187 port->schedTimingResp(pkt, curTick() + rp->m_ruby_system->clockPeriod()); 249 schedTimingResp(pkt, curTick()); 267 curTick() + rs->clockPeriod()); 557 schedTimingResp(pkt, curTick());
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/gem5/src/dev/x86/ |
H A D | intdev.hh | 121 schedTimingReq(pkt, curTick() + latency);
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/gem5/src/arch/arm/tracers/ |
H A D | tarmac_record.cc | 414 curTick(), /* Tick time */ 434 curTick(), /* Tick time */ 452 curTick(), /* Tick time */
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/gem5/src/mem/cache/tags/ |
H A D | base.cc | 120 warmupCycle = curTick(); 155 assert(blk.tickInserted <= curTick()); 156 Tick age = curTick() - blk.tickInserted;
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/gem5/configs/common/ |
H A D | Simulation.py | 238 exit_event = m5.simulate(when - m5.curTick()) 241 exit_event = m5.simulate(when - m5.curTick()) 262 exit_event = m5.simulate(sim_ticks - m5.curTick()) 270 exit_event = m5.simulate(maxtick - m5.curTick()) 283 exit_event = m5.simulate(maxtick - m5.curTick()) 390 print('Exiting @ tick %i because %s' % (m5.curTick(), exit_cause)) 410 print('Exiting @ tick %i because %s' % (m5.curTick(), exit_cause)) 429 if (maxtick - m5.curTick()) <= switch_freq: 430 exit_event = m5.simulate(maxtick - m5.curTick()) 669 print("Switch at curTick coun [all...] |
/gem5/src/cpu/o3/ |
H A D | thread_context_impl.hh | 96 thread->lastActivate = curTick(); 118 thread->lastActivate = curTick(); 119 thread->lastSuspend = curTick();
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/gem5/src/cpu/testers/memtest/ |
H A D | memtest.cc | 121 schedule(tickEvent, curTick()); 163 req->getPaddr(), blockAlign(req->getPaddr()), curTick(), 172 name(), numReads, numWrites, curTick());
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/gem5/src/cpu/trace/ |
H A D | trace_cpu.cc | 166 "at %d.\n", curTick() + icacheGen.tickDelta()); 167 schedule(icacheNextEvent, curTick() + icacheGen.tickDelta()); 211 schedule(*execCompleteEvent, curTick()); 462 // tick later than curTick or the end of readyList is reached 463 while (free_itr->execTick <= curTick() && free_itr != readyList.end()) { 603 curTick()); 620 dataLastTick = curTick(); 791 // tick greater than or equal to curTick. But a new dep-free node might 1134 instLastTick = curTick(); 1186 " event @%lli.\n", curTick()); [all...] |
/gem5/src/mem/ruby/structures/ |
H A D | CacheMemory.cc | 173 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 201 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 285 m_replacementPolicy_ptr->touch(cacheSet, i, curTick()); 351 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 359 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 371 touch(cacheSet, loc, curTick(), occupancy); 374 touch(cacheSet, loc, curTick());
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/gem5/src/arch/mips/ |
H A D | mt.hh | 147 curTick(), tc->threadId(), tc->getCpuPtr()->name(), 165 curTick(), tc->threadId(), tc->getCpuPtr()->name(), restartPC); 275 curTick(), tc->threadId());
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/gem5/src/dev/net/ |
H A D | sinic.cc | 461 Tick when = curTick(); 497 cpuIntrPost(curTick()); 514 assert(when >= curTick()); 515 assert(intrTick >= curTick() || intrTick == 0); 529 if (intrTick < curTick()) { 530 intrTick = curTick(); 547 assert(intrTick == curTick()); 603 cpuIntrPost(curTick()); 726 if (rxKickTick > curTick()) { 1041 if (txKickTick > curTick()) { [all...] |