Searched refs:curTick (Results 176 - 200 of 213) sorted by relevance
123456789
/gem5/src/base/ |
H A D | cp_annotate.cc | 178 warn("Got null SM at tick %d\n", curTick()); 290 warn("State machine stack not unwinding correctly at %d\n", curTick()); 333 warn("BAD state encountered: at cycle %d: %s\n", curTick(), st); 702 curTick(), size, q, qBytes[qi-1]); 705 curTick(), size, q, qBytes[qi-1]); 827 an->time = curTick();
|
H A D | cp_annotate.hh | 442 warn("BAD state encountered: at cycle %d: %s\n", curTick(), st);
|
H A D | remote_gdb.cc | 365 curTick(), name(), _port);
|
/gem5/src/gpu-compute/ |
H A D | compute_unit.cc | 680 curTick() + computeUnit->resp_tick_latency); 769 tlbCycles -= curTick(); 855 schedule(mem_req_event, curTick() + req_tick_latency); 937 schedule(mem_req_event, curTick() + req_tick_latency); 1077 computeUnit->tlbCycles += curTick(); 1231 computeUnit->schedule(mem_req_event, curTick() +
|
/gem5/src/dev/arm/ |
H A D | generic_timer.cc | 65 _resetTick = curTick(); 136 curTick() + (_counterLimit - value()) * period);
|
H A D | smmu_v3_transl.cc | 123 Tick resumeTick = curTick(); 160 recvTick = curTick(); 277 Tick ptwStartTick = curTick(); 288 smmu.ptwTimeDist.sample(curTick() - ptwStartTick); 1238 smmu.translationTimeDist.sample(curTick() - recvTick);
|
H A D | hdlcd.cc | 233 schedule(virtRefreshEvent, (curTick() + virtRefreshRate));
|
H A D | gic_v2.cc | 827 postFiq(cpu, curTick() + intLatency); 829 postInt(cpu, curTick() + intLatency);
|
/gem5/src/mem/ruby/system/ |
H A D | Sequencer.cc | 461 curTick(), m_version, "Seq", 645 curTick(), m_version, "Seq", "Begin", "", "",
|
/gem5/src/cpu/simple/ |
H A D | atomic.cc | 730 stall_ticks += clockEdge(syscallRetryLatency) - curTick(); 768 reschedule(tickEvent, curTick() + latency, true);
|
/gem5/configs/splash2/ |
H A D | cluster.py | 303 print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause())
|
/gem5/tests/configs/ |
H A D | gpu-ruby.py | 82 print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause())
|
/gem5/util/tlm/src/ |
H A D | sc_master_port.cc | 175 assert(curTick() == sc_core::sc_time_stamp().value());
|
/gem5/src/mem/ruby/network/ |
H A D | MessageBuffer.cc | 238 m_stall_time = curTick() - message->getTime();
|
/gem5/src/arch/arm/ |
H A D | semihosting.cc | 517 return retOK(curTick() / (SimClock::Int::s / 100)); 524 return retOK(timeBase + round(curTick() / SimClock::Float::s)); 663 const uint64_t tick = semiTick(curTick());
|
H A D | intregs.hh | 495 curTick(), reg, mode);
|
/gem5/src/cpu/o3/ |
H A D | fetch_impl.hh | 711 lastIcacheStall[tid] = curTick(); 1131 cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid), 1342 instruction->fetchTick = curTick();
|
H A D | lsq_unit_impl.hh | 809 cpu->schedule(wb, curTick() + 1); 1024 curTick() - store_inst->fetchTick;
|
/gem5/src/mem/ruby/network/garnet2.0/ |
H A D | NetworkInterface.cc | 424 name(), vnet, curTick());
|
/gem5/src/dev/ |
H A D | dma_device.cc | 97 device->schedule(state->completionEvent, curTick() + delay);
|
/gem5/src/sim/ |
H A D | system.cc | 467 Tick samp = curTick() - lastWorkItemStarted[p];
|
/gem5/src/cpu/kvm/ |
H A D | base.cc | 169 schedule(startupEvent, curTick()); 640 curEventQueue()->nextTick() - curTick() : 0);
|
/gem5/src/arch/arm/tracers/ |
H A D | tarmac_parser.cc | 749 outs << "\nMismatch between gem5 and TARMAC trace @ " << dec << curTick() 870 mainEventQueue[0]->schedule(event, curTick());
|
/gem5/src/mem/ |
H A D | coherent_xbar.cc | 486 slavePorts[slave_port_id]->schedTimingResp(pkt, curTick() + latency); 670 slavePorts[dest_port_id]->schedTimingResp(pkt, curTick() + latency);
|
/gem5/src/mem/cache/ |
H A D | base.cc | 156 owner.schedule(sendRetryEvent, curTick() + 1); 291 // ready yet (i.e. time > curTick()), we don't want to 445 Tick miss_latency = curTick() - initial_tgt->recvTime; 610 schedule(writebackTempBlockAtomicEvent, curTick()); 787 return allocateMissBuffer(pkt, curTick(), false); 1007 const Tick tick = curTick() + delay;
|
Completed in 84 milliseconds
123456789