Searched refs:control (Results 26 - 31 of 31) sorted by relevance

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/gem5/src/dev/arm/
H A Dpl011.hh152 uint16_t control; member in class:Pl011
162 /** Line control register. Not used for anything but reporting
H A Dgeneric_timer.cc164 DPRINTF(Timer, "Causing interrupt in control\n");
449 return core.physNS.control();
475 return core.virt.control();
480 return core.physS.control();
493 return core.hyp.control();
633 warn("Reading from unimplemented control register (0x%x)\n", addr);
669 warn("Write to unimplemented control register (0x%x)\n", addr);
743 return physTimer.control();
755 return virtTimer.control();
H A Dgeneric_timer.hh72 /// Kernel event stream control register
74 /// Hypervisor event stream control register
132 /// Value of the control register ({CNTP/CNTHP/CNTV}_CTL).
170 /// Sets the control register.
171 uint32_t control() const { return _control; } function in class:ArchTimer
/gem5/util/tlm/src/
H A Dsc_master_port.cc421 auto* port = new SCMasterPort(name, port_data, owner, control);
423 control.registerMasterPort(port_data, port);
H A Dsc_slave_port.cc395 control.registerSlavePort(port_data, port);
/gem5/src/arch/hsail/
H A DBrig_new.hpp1229 BrigControlDirective16_t control; member in struct:BrigDirectiveControl

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