| /gem5/src/systemc/tests/systemc/compliance_1666/test00/ |
| H A D | test00.cpp | 216 sc_in_clk clk;
member in struct:CM
224 SC_CTHREAD(CT, clk.pos());
280 sc_signal<bool> clk, reset;
local
287 cm->clk(clk);
297 clk = false;
300 clk = true;
302 clk = false;
305 clk = true;
307 clk
[all...] |
| /gem5/src/systemc/tests/systemc/examples/updown/ |
| H A D | updown.cpp | 9 sc_in_clk clk; local
26 sensitive << clk.pos();
103 up_down_0.clk(clock);
|
| /gem5/src/systemc/tests/systemc/misc/sim_tests/cycle_dw8051_demo/ |
| H A D | cycle_model.h | 140 sc_in_clk clk; local
220 clk(CLK);
222 sensitive << clk; local
|
| H A D | cycle_model.cpp | 93 #define AT_POSEDGE(CLK) wait(); while(!clk.posedge()) wait();
94 #define AT_NEGEDGE(CLK) wait(); while(!clk.negedge()) wait();
1099 AT_POSEDGE(clk);
1100 AT_POSEDGE(clk);
1101 AT_POSEDGE(clk);
1102 AT_POSEDGE(clk);
1132 AT_POSEDGE(clk);
1158 AT_NEGEDGE(clk);
1162 AT_POSEDGE(clk);
1187 AT_POSEDGE(clk);
[all...] |
| /gem5/src/systemc/tests/systemc/misc/synth/circle/ |
| H A D | circ48.h | 44 sc_in_clk clk; local
67 clk( clk_ );
75 SC_CTHREAD( entry, clk.pos() );
|
| H A D | tb.h | 44 sc_in_clk clk; local
65 clk( clk_ );
72 SC_CTHREAD( entry, clk.neg() );
|
| /gem5/src/systemc/tests/systemc/misc/user_guide/newsched/test1/ |
| H A D | test1.cpp | 52 sc_in<bool> clk; local
65 SC_CTHREAD( entry, clk.pos() );
66 clk(CLK);
|
| /gem5/src/systemc/tests/systemc/misc/user_guide/newsched/test2/ |
| H A D | test2.cpp | 51 sc_in<bool> clk; local
64 clk(CLK);
65 SC_CTHREAD( entry, clk.pos() );
|
| /gem5/src/systemc/tests/systemc/misc/user_guide/newsched/test6/ |
| H A D | test6.cpp | 117 sc_in<bool> clk; local
126 clk(CLK);
127 SC_CTHREAD( entry, clk.pos() );
|
| /gem5/src/systemc/tests/systemc/misc/user_guide/newsched/test7/ |
| H A D | test7.cpp | 119 sc_in<bool> clk; local
128 clk(CLK);
129 SC_CTHREAD( entry, clk.pos() );
|
| /gem5/src/systemc/tests/systemc/misc/user_guide/newsched/test8/ |
| H A D | test8.cpp | 128 sc_in<bool> clk; local
137 clk(CLK);
138 SC_CTHREAD( entry, clk.pos() );
|
| /gem5/src/systemc/tests/systemc/misc/stars/star110089/ |
| H A D | star110089.cpp | 119 sc_in_clk clk; local
157 SC_CTHREAD(lp_write_buf_body, clk.pos());
159 SC_CTHREAD(check_read_address, clk.pos());
|
| /gem5/src/systemc/tests/systemc/misc/synth/bubble/ |
| H A D | bubble.h | 48 sc_in_clk clk; local
93 clk(TICK_P);
94 SC_CTHREAD( entry, clk.pos() );
|
| H A D | stim.h | 48 sc_in_clk clk; local
94 clk(TICK_P);
95 SC_CTHREAD( entry, clk.neg() );
|
| /gem5/src/systemc/tests/systemc/misc/unit/control/wait/ |
| H A D | wait.cpp | 72 SC_CTOR(Wait) : clk( "clk", 10, SC_US, 0.5, 100, SC_US) {
74 sensitive << clk; local
85 SC_WAIT(); // Wait for clk
94 sc_core::sc_clock clk; local
|
| /gem5/src/systemc/tests/systemc/compliance_1666/test208/ |
| H A D | test208.cpp | 182 sc_in_clk clk;
local
189 : clk("clk"), p("p"), xp("xp"), sig("sig")
195 SC_CTHREAD(p2,clk);
204 sc_assert (strcmp(children[0]->name(), "top.clk") == 0);
231 sc_signal<bool> clk;
local
233 top.clk(clk);
|
| /gem5/ext/drampower/src/ |
| H A D | MemoryPowerModel.h | 74 double clk);
84 double clk,
|
| /gem5/src/systemc/tests/systemc/examples/isqrt/ |
| H A D | isqrt.cpp | 197 sc_clock clk; local
209 (*isqp)(reset, clk,
|
| /gem5/src/systemc/tests/systemc/misc/stars/star109218-2/ |
| H A D | star109218-2.cpp | 77 my_mult(clk.read(), a.range(7,0), a.range(15,8), result);
|
| /gem5/src/systemc/tests/systemc/compliance_1666/test203a/ |
| H A D | test203a.cpp | 46 sc_in_clk clk;
local
53 SC_CTHREAD(CT, clk.pos());
245 sc_clock clk;
member in struct:Top
249 m->clk(clk);
|
| /gem5/configs/common/ |
| H A D | HMC.py | 301 clk = '100GHz'
311 cd = SrcClockDomain(clock=clk, voltage_domain=vd)
353 clk = opt.link_controller_frequency
355 scd = SrcClockDomain(clock=clk, voltage_domain=vd)
413 clk = opt.xbar_frequency
415 scd = SrcClockDomain(clock=clk, voltage_domain=vd)
|
| /gem5/configs/example/ |
| H A D | hmctest.py | 57 clk = '100GHz'
59 system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
|
| /gem5/src/systemc/tests/systemc/datatypes/misc/concat/test02/ |
| H A D | test02.cpp | 156 SC_CTHREAD(sync, clk.pos());
171 sc_in_clk clk; local
193 x.clk(clock);
|
| /gem5/src/dev/arm/ |
| H A D | rv_ctrl.cc | 70 Tick clk; local
71 clk = SimClock::Float::MHz * curTick() * 24;
72 pkt->setLE((uint32_t)(clk));
|
| /gem5/src/systemc/tests/systemc/1666-2011-compliance/async_reset/ |
| H A D | async_reset.cpp | 45 clk_port.bind(clk);
59 opt.set_sensitivity( &clk );
83 clk.write(false);
97 sc_signal<bool> clk; member in struct:Top
396 wait(clk.default_event());
512 clk.write( !clk.read() );
517 clk.write(0);
519 clk.write(1);
|