Searched refs:bits (Results 101 - 120 of 120) sorted by relevance

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/gem5/src/arch/arm/insts/
H A Dmacromem.cc68 bool copy_base = (bits(reglist, rn) && load) || !ones;
69 bool force_user = user & !bits(reglist, 15);
70 bool exception_ret = user & bits(reglist, 15);
71 bool pc_temp = load && writeback && bits(reglist, 15);
106 !(mem_ops == 2 && bits(regs,INTREG_PC) && exception_ret)) {
108 // Find 2 set register bits (clear them after finding)
113 while (!bits(regs, reg)) reg++;
118 while (!bits(regs, reg)) reg++;
148 while (!bits(regs, reg)) reg++;
/gem5/src/arch/x86/
H A Dtlb.cc208 if (bits(configAddress, 31, 31)) {
317 Addr offset = bits(vaddr - base, size - 1, 0);
396 // the first place. We'll assume the reserved bits are
H A Ddecoder.cc277 if (emi.mode.submode != SixtyFourBitMode && bits(nextByte, 7, 6) == 0x3) {
318 if (emi.mode.submode != SixtyFourBitMode && bits(nextByte, 7, 6) == 0x3) {
655 //need to have the immediate sign extended to 64 bits.
/gem5/src/dev/arm/
H A Dtimer_sp804.cc186 time *= bits(val,15,0);
H A Dsmmu_v3_transl.cc1348 bits(sid, 32, split) * sizeof(l2_ptr);
1360 unsigned index = bits(sid, split-1, 0);
1416 bits(ssid, 24, split) * sizeof(l2_ptr);
1427 cd_addr = l2_ptr + bits(ssid, split-1, 0) * sizeof(cd);
H A Dgic_v3_redistributor.cc152 * (GICR_CTLR.DPG* bits are supported)
182 return 0x92; // Part number, bits[7:0]
186 uint8_t des_0 = 0xB; // JEP106 identification code, bits[3:0]
187 uint8_t part_1 = 0x4; // Part number, bits[11:8]
194 uint8_t des_1 = 0x3; // JEP106 identification code, bits[6:4]
346 // OuterCache, bits [58:56]
348 // Physical_Address, bits [51:12]
351 // Shareability, bits [11:10]
353 // InnerCache, bits [9:7]
355 // IDbits, bits [
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/gem5/src/base/
H A Daddr_range.hh63 * allowing a number of bits of the address, at an arbitrary bit
64 * position, to be used as interleaving bits with an associated
67 * hashing by specifying a set of bits to XOR with before matching.
83 * Each mask determines the bits we need to xor to get one bit of
103 * bits that are xored to determine one bit of the sel value,
133 "Match value %d does not fit in %d interleaving bits\n",
156 * @param _intlv_high_bit The MSB of the intlv bits (disabled if 0)
168 "Match value %d does not fit in %d interleaving bits\n",
171 // ignore the XOR bits if not interleaving
178 "%d bits apar
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/gem5/src/dev/x86/
H A Di8042.cc182 panic_if(bits(data, 0) != 1, "Reset bit should be 1");
/gem5/src/dev/pci/
H A Ddevice.cc403 // This could also clear some of the error bits in the Status
472 paramOut(cp, csprintf("msix_pba[%d].bits", i),
473 msix_pba[i].bits);
553 paramIn(cp, csprintf("msix_pba[%d].bits", i),
554 msix_pba[i].bits);
/gem5/ext/googletest/googletest/include/gtest/internal/
H A Dgtest-internal.h251 // For float, there are 8 exponent bits and 23 fraction bits.
253 // For double, there are 11 exponent bits and 52 fraction bits.
270 // # of bits in a number.
273 // # of fraction bits in a number.
277 // # of exponent bits in a number.
283 // The mask for the fraction bits.
287 // The mask for the exponent bits.
298 // bits
317 ReinterpretBits(const Bits bits) argument
334 const Bits &bits() const { return u_.bits_; } function in class:testing::internal::FloatingPoint
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/gem5/src/arch/arm/
H A Dtlb.cc350 // D5.7.2: Sign-extend address to 64 bits
690 // The 'ap' variable is AP[2:0] or {AP[2,1],1b'0}, i.e. always three bits
868 // In stage 2 we use the hypervisor access permission bits.
1326 asid = bits(ttbr_asid,
1345 vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48);
1379 asid = bits(ttbr_asid, 55, 48);
1394 vmid = bits(tc->readMiscReg(MISCREG_VTTBR), 55, 48);
/gem5/src/cpu/pred/
H A Dmultiperspective_perceptron.cc134 MultiperspectivePerceptron::setExtraBits(int bits) argument
136 extrabits = bits;
226 // if a table doesn't have a size yet, give it one and count those bits
229 (specs[i]->width + (n_sign_bits - 1)); // extra sign bits
235 DPRINTF(Branch, "%d bits of metadata so far, %d left out of "
237 DPRINTF(Branch, "table size is %d bits, %d entries for 5 bit, %d entries "
241 DPRINTF(Branch, "%d total bits (%0.2fKB)\n", totalbits,
H A Dmultiperspective_perceptron.hh57 /** pc of the branch, shifted 2 bits to the right */
173 /** Size in bits of each history entry */
200 /** Returns the number of bits of each local history entry */
206 /** Size in bits required by all history entries */
225 /** Pre-assigned size in bits assigned to this feature */
227 /** Width of the table in bits */
243 * @param pc2 address of the branch shifted 2 bits to the right
354 /** runtime values and data used to count the size in bits */
413 * Computes the size in bits of the structures needed to keep track
510 // so the number of bits betwee
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/gem5/src/base/loader/
H A Delf_object.cc110 arch = bits(ehdr.e_entry, 0) ? Thumb : Arm;
/gem5/src/gpu-compute/
H A Dgpu_tlb.cc163 * The least significant bits are simply masked
626 if (bits(configAddress, 31, 31)) {
754 // default address size is 64 bits, overridable to 32.
764 Addr offset = bits(vaddr - base, size - 1, 0);
846 // the first place. We'll assume the reserved bits are
1141 // the first place. We'll assume the reserved bits are
/gem5/ext/googletest/googletest/src/
H A Dgtest.cc1723 // A Unicode code-point can have upto 21 bits, and is encoded in UTF-8
1727 // 0 - 7 bits 0xxxxxxx
1728 // 8 - 11 bits 110xxxxx 10xxxxxx
1729 // 12 - 16 bits 1110xxxx 10xxxxxx 10xxxxxx
1730 // 17 - 21 bits 11110xxx 10xxxxxx 10xxxxxx 10xxxxxx
1744 // Chops off the n lowest bits from a bit pattern. Returns the n
1745 // lowest bits. As a side effect, the original bit pattern will be
1746 // shifted to the right by n bits.
1747 inline UInt32 ChopLowBits(UInt32* bits, int n) { argument
1748 const UInt32 low_bits = *bits
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/gem5/ext/googletest/googletest/test/
H A Dgtest_unittest.cc416 // 32 bits, even when 64-bit integer types are available. We have to
541 // Tests that Unicode code-points that have 8 to 11 bits are encoded
555 // Tests that Unicode code-points that have 12 to 16 bits are encoded
568 // Tests in this group require a wchar_t to hold > 16 bits, and thus
572 // Tests that Unicode code-points that have 17 to 21 bits are encoded
608 // Tests that Unicode code-points that have 8 to 11 bits are encoded
621 // Tests that Unicode code-points that have 12 to 16 bits are encoded
647 // Tests that Unicode code-points that have 17 to 21 bits are encoded
2694 // The bits that represent 0.0.
2695 const Bits zero_bits = Floating(0).bits();
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/gem5/ext/googletest/googlemock/test/
H A Dgmock-matchers_test.cc2712 zero_bits_(Floating(0).bits()),
2713 one_bits_(Floating(1).bits()),
2714 infinity_bits_(Floating(Floating::Infinity()).bits()),
2783 const Bits zero_bits_; // The bits that represent 0.0.
2784 const Bits one_bits_; // The bits that represent 1.0.
2785 const Bits infinity_bits_; // The bits that represent +infinity.
/gem5/src/dev/net/
H A Di8254xGBe.cc160 // Some work may need to be done here based for the pci COMMAND bits.
498 regs.icr = ~bits(val,30,0) & regs.icr();
/gem5/src/mem/
H A Ddram_ctrl.cc213 // for the interleavings with channel bits in the bottom,
218 // lower-order column bits as the least-significant bits
315 // always the top bits, and check before creating the DRAMPacket
322 // we have removed the lowest order address bits that denote the
325 // the lowest order bits denote the column to ensure that
332 // after the channel bits, get the bank bits to interleave
337 // after the bank, we get the rank bits which thus interleaves
342 // lastly, get the row bits, n
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